mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
620 lines
20 KiB
C
620 lines
20 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Machine Specific Values for TRATS board based on EXYNOS4210
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*
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* Copyright (C) 2011 Samsung Electronics
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* Heungjun Kim <riverful.kim@samsung.com>
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*/
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#ifndef _TRATS_SETUP_H
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#define _TRATS_SETUP_H
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#include <config.h>
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#include <asm/arch/cpu.h>
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/* CLK_SRC_CPU: APLL(1), MPLL(1), CORE(0), HPM(0) */
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#define MUX_HPM_SEL_MOUTAPLL 0x0
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#define MUX_HPM_SEL_SCLKMPLL 0x1
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#define MUX_CORE_SEL_MOUTAPLL 0x0
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#define MUX_CORE_SEL_SCLKMPLL 0x1
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#define MUX_MPLL_SEL_FILPLL 0x0
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#define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
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#define MUX_APLL_SEL_FILPLL 0x0
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#define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
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#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \
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| (MUX_CORE_SEL_MOUTAPLL << 16) \
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| (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
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| (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
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/* CLK_DIV_CPU0 */
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#define APLL_RATIO 0x0
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#define PCLK_DBG_RATIO 0x1
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#define ATB_RATIO 0x3
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#define PERIPH_RATIO 0x3
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#define COREM1_RATIO 0x7
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#define COREM0_RATIO 0x3
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#define CORE_RATIO 0x0
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#define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \
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| (PCLK_DBG_RATIO << 20) \
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| (ATB_RATIO << 16) \
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| (PERIPH_RATIO << 12) \
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| (COREM1_RATIO << 8) \
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| (COREM0_RATIO << 4) \
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| (CORE_RATIO << 0))
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/* CLK_DIV_CPU1 */
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#define HPM_RATIO 0x0
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#define COPY_RATIO 0x3
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#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO))
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/* CLK_DIV_DMC0 */
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#define CORE_TIMERS_RATIO 0x1
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#define COPY2_RATIO 0x3
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#define DMCP_RATIO 0x1
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#define DMCD_RATIO 0x1
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#define DMC_RATIO 0x1
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#define DPHY_RATIO 0x1
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#define ACP_PCLK_RATIO 0x1
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#define ACP_RATIO 0x3
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#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \
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| (COPY2_RATIO << 24) \
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| (DMCP_RATIO << 20) \
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| (DMCD_RATIO << 16) \
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| (DMC_RATIO << 12) \
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| (DPHY_RATIO << 8) \
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| (ACP_PCLK_RATIO << 4) \
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| (ACP_RATIO << 0))
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/* CLK_DIV_DMC1 */
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#define DPM_RATIO 0x1
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#define DVSEM_RATIO 0x1
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#define PWI_RATIO 0x1
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#define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \
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| (DVSEM_RATIO << 16) \
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| (PWI_RATIO << 8))
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/* CLK_SRC_TOP0 */
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#define MUX_ONENAND_SEL_ACLK_133 0x0
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#define MUX_ONENAND_SEL_ACLK_160 0x1
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#define MUX_ACLK_133_SEL_SCLKMPLL 0x0
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#define MUX_ACLK_133_SEL_SCLKAPLL 0x1
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#define MUX_ACLK_160_SEL_SCLKMPLL 0x0
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#define MUX_ACLK_160_SEL_SCLKAPLL 0x1
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#define MUX_ACLK_100_SEL_SCLKMPLL 0x0
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#define MUX_ACLK_100_SEL_SCLKAPLL 0x1
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#define MUX_ACLK_200_SEL_SCLKMPLL 0x0
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#define MUX_ACLK_200_SEL_SCLKAPLL 0x1
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#define MUX_VPLL_SEL_FINPLL 0x0
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#define MUX_VPLL_SEL_FOUTVPLL 0x1
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#define MUX_EPLL_SEL_FINPLL 0x0
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#define MUX_EPLL_SEL_FOUTEPLL 0x1
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#define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
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#define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
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#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_160 << 28) \
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| (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
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| (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
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| (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
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| (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
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| (MUX_VPLL_SEL_FOUTVPLL << 8) \
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| (MUX_EPLL_SEL_FOUTEPLL << 4) \
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| (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
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/* CLK_DIV_TOP */
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#define ONENAND_RATIO 0x0
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#define ACLK_133_RATIO 0x5
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#define ACLK_160_RATIO 0x4
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#define ACLK_100_RATIO 0x7
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#define ACLK_200_RATIO 0x3
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#define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \
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| (ACLK_133_RATIO << 12)\
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| (ACLK_160_RATIO << 8) \
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| (ACLK_100_RATIO << 4) \
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| (ACLK_200_RATIO << 0))
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/* CLK_DIV_LEFTBUS */
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#define GPL_RATIO 0x1
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#define GDL_RATIO 0x3
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#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO))
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/* CLK_DIV_RIGHTBUS */
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#define GPR_RATIO 0x1
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#define GDR_RATIO 0x3
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#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO))
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/* CLK_SRS_FSYS: 6 = SCLKMPLL */
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#define SATA_SEL_SCLKMPLL 0
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#define SATA_SEL_SCLKAPLL 1
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#define MMC_SEL_XXTI 0
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#define MMC_SEL_XUSBXTI 1
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#define MMC_SEL_SCLK_HDMI24M 2
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#define MMC_SEL_SCLK_USBPHY0 3
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#define MMC_SEL_SCLK_USBPHY1 4
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#define MMC_SEL_SCLK_HDMIPHY 5
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#define MMC_SEL_SCLKMPLL 6
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#define MMC_SEL_SCLKEPLL 7
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#define MMC_SEL_SCLKVPLL 8
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#define MMCC0_SEL MMC_SEL_SCLKMPLL
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#define MMCC1_SEL MMC_SEL_SCLKMPLL
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#define MMCC2_SEL MMC_SEL_SCLKMPLL
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#define MMCC3_SEL MMC_SEL_SCLKMPLL
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#define MMCC4_SEL MMC_SEL_SCLKMPLL
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#define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \
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| (MMCC4_SEL << 16) \
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| (MMCC3_SEL << 12) \
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| (MMCC2_SEL << 8) \
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| (MMCC1_SEL << 4) \
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| (MMCC0_SEL << 0))
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/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
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/* CLK_DIV_FSYS1: 800(MPLL) / (15 + 1) */
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#define MMC0_RATIO 0xF
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#define MMC0_PRE_RATIO 0x0
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#define MMC1_RATIO 0xF
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#define MMC1_PRE_RATIO 0x0
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#define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \
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| (MMC1_RATIO << 16) \
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| (MMC0_PRE_RATIO << 8) \
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| (MMC0_RATIO << 0))
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/* CLK_DIV_FSYS2: 800(MPLL) / (15 + 1) */
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#define MMC2_RATIO 0xF
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#define MMC2_PRE_RATIO 0x0
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#define MMC3_RATIO 0xF
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#define MMC3_PRE_RATIO 0x0
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#define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \
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| (MMC3_RATIO << 16) \
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| (MMC2_PRE_RATIO << 8) \
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| (MMC2_RATIO << 0))
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/* CLK_DIV_FSYS3: 800(MPLL) / (15 + 1) */
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#define MMC4_RATIO 0xF
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#define MMC4_PRE_RATIO 0x0
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#define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \
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| (MMC4_RATIO << 0))
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/* CLK_SRC_PERIL0 */
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#define UART_SEL_XXTI 0
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#define UART_SEL_XUSBXTI 1
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#define UART_SEL_SCLK_HDMI24M 2
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#define UART_SEL_SCLK_USBPHY0 3
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#define UART_SEL_SCLK_USBPHY1 4
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#define UART_SEL_SCLK_HDMIPHY 5
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#define UART_SEL_SCLKMPLL 6
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#define UART_SEL_SCLKEPLL 7
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#define UART_SEL_SCLKVPLL 8
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#define UART0_SEL UART_SEL_SCLKMPLL
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#define UART1_SEL UART_SEL_SCLKMPLL
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#define UART2_SEL UART_SEL_SCLKMPLL
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#define UART3_SEL UART_SEL_SCLKMPLL
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#define UART4_SEL UART_SEL_SCLKMPLL
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#define UART5_SEL UART_SEL_SCLKMPLL
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#define CLK_SRC_PERIL0_VAL ((UART5_SEL << 16) \
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| (UART4_SEL << 12) \
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| (UART3_SEL << 12) \
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| (UART2_SEL << 8) \
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| (UART1_SEL << 4) \
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| (UART0_SEL << 0))
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/* SCLK_UART[0-4] = MOUTUART[0-4] / (UART[0-4]_RATIO + 1) */
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/* CLK_DIV_PERIL0 */
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#define UART0_RATIO 7
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#define UART1_RATIO 7
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#define UART2_RATIO 7
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#define UART3_RATIO 4
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#define UART4_RATIO 7
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#define UART5_RATIO 7
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#define CLK_DIV_PERIL0_VAL ((UART5_RATIO << 16) \
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| (UART4_RATIO << 12) \
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| (UART3_RATIO << 12) \
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| (UART2_RATIO << 8) \
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| (UART1_RATIO << 4) \
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| (UART0_RATIO << 0))
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/* CLK_DIV_PERIL3 */
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#define SLIMBUS_RATIO 0x0
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#define PWM_RATIO 0x8
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#define CLK_DIV_PERIL3_VAL ((SLIMBUS_RATIO << 4) \
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| (PWM_RATIO << 0))
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/* Required period to generate a stable clock output */
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/* PLL_LOCK_TIME */
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#define PLL_LOCKTIME 0x1C20
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/* PLL Values */
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#define DISABLE 0
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#define ENABLE 1
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#define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\
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| (mdiv << 16) \
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| (pdiv << 8) \
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| (sdiv << 0))
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/* APLL_CON0: 800MHz */
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#define APLL_MDIV 0xC8
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#define APLL_PDIV 0x6
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#define APLL_SDIV 0x1
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#define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
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/* APLL_CON1 */
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#define APLL_AFC_ENB 0x1
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#define APLL_AFC 0x1C
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#define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
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/* MPLL_CON0: 800MHz */
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#define MPLL_MDIV 0xC8
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#define MPLL_PDIV 0x6
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#define MPLL_SDIV 0x1
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#define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
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/* MPLL_CON1 */
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#define MPLL_AFC_ENB 0x1
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#define MPLL_AFC 0x1C
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#define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
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/* EPLL_CON0: 96MHz */
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#define EPLL_MDIV 0x30
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#define EPLL_PDIV 0x3
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#define EPLL_SDIV 0x2
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#define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
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/* EPLL_CON1 */
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#define EPLL_K 0x0
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#define EPLL_CON1_VAL (EPLL_K >> 0)
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/* VPLL_CON0: 108MHz */
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#define VPLL_MDIV 0x35
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#define VPLL_PDIV 0x3
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#define VPLL_SDIV 0x2
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#define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
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/* VPLL_CON1 */
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#define VPLL_SSCG_EN DISABLE
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#define VPLL_SEL_PF_DN_SPREAD 0x0
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#define VPLL_MRR 0x11
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#define VPLL_MFR 0x0
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#define VPLL_K 0x400
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#define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\
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| (VPLL_SEL_PF_DN_SPREAD << 29) \
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| (VPLL_MRR << 24) \
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| (VPLL_MFR << 16) \
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| (VPLL_K << 0))
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/* CLOCK GATE */
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#define CLK_DIS 0x0
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#define CLK_EN 0x1
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#define BIT_CAM_CLK_PIXELASYNCM1 18
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#define BIT_CAM_CLK_PIXELASYNCM0 17
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#define BIT_CAM_CLK_PPMUCAMIF 16
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#define BIT_CAM_CLK_QEFIMC3 15
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#define BIT_CAM_CLK_QEFIMC2 14
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#define BIT_CAM_CLK_QEFIMC1 13
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#define BIT_CAM_CLK_QEFIMC0 12
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#define BIT_CAM_CLK_SMMUJPEG 11
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#define BIT_CAM_CLK_SMMUFIMC3 10
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#define BIT_CAM_CLK_SMMUFIMC2 9
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#define BIT_CAM_CLK_SMMUFIMC1 8
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#define BIT_CAM_CLK_SMMUFIMC0 7
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#define BIT_CAM_CLK_JPEG 6
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#define BIT_CAM_CLK_CSIS1 5
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#define BIT_CAM_CLK_CSIS0 4
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#define BIT_CAM_CLK_FIMC3 3
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#define BIT_CAM_CLK_FIMC2 2
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#define BIT_CAM_CLK_FIMC1 1
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#define BIT_CAM_CLK_FIMC0 0
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#define CLK_GATE_IP_CAM_ALL_EN ((CLK_EN << BIT_CAM_CLK_PIXELASYNCM1)\
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| (CLK_EN << BIT_CAM_CLK_PIXELASYNCM0)\
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| (CLK_EN << BIT_CAM_CLK_PPMUCAMIF)\
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| (CLK_EN << BIT_CAM_CLK_QEFIMC3)\
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| (CLK_EN << BIT_CAM_CLK_QEFIMC2)\
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| (CLK_EN << BIT_CAM_CLK_QEFIMC1)\
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| (CLK_EN << BIT_CAM_CLK_QEFIMC0)\
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| (CLK_EN << BIT_CAM_CLK_SMMUJPEG)\
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| (CLK_EN << BIT_CAM_CLK_SMMUFIMC3)\
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| (CLK_EN << BIT_CAM_CLK_SMMUFIMC2)\
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| (CLK_EN << BIT_CAM_CLK_SMMUFIMC1)\
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| (CLK_EN << BIT_CAM_CLK_SMMUFIMC0)\
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| (CLK_EN << BIT_CAM_CLK_JPEG)\
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| (CLK_EN << BIT_CAM_CLK_CSIS1)\
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| (CLK_EN << BIT_CAM_CLK_CSIS0)\
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| (CLK_EN << BIT_CAM_CLK_FIMC3)\
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| (CLK_EN << BIT_CAM_CLK_FIMC2)\
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| (CLK_EN << BIT_CAM_CLK_FIMC1)\
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| (CLK_EN << BIT_CAM_CLK_FIMC0))
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#define CLK_GATE_IP_CAM_ALL_DIS ~CLK_GATE_IP_CAM_ALL_EN
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#define BIT_VP_CLK_PPMUTV 5
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#define BIT_VP_CLK_SMMUTV 4
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#define BIT_VP_CLK_HDMI 3
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#define BIT_VP_CLK_TVENC 2
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#define BIT_VP_CLK_MIXER 1
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#define BIT_VP_CLK_VP 0
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#define CLK_GATE_IP_VP_ALL_EN ((CLK_EN << BIT_VP_CLK_PPMUTV)\
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| (CLK_EN << BIT_VP_CLK_SMMUTV)\
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| (CLK_EN << BIT_VP_CLK_HDMI)\
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| (CLK_EN << BIT_VP_CLK_TVENC)\
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| (CLK_EN << BIT_VP_CLK_MIXER)\
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| (CLK_EN << BIT_VP_CLK_VP))
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#define CLK_GATE_IP_VP_ALL_DIS ~CLK_GATE_IP_VP_ALL_EN
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#define BIT_MFC_CLK_PPMUMFC_R 4
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#define BIT_MFC_CLK_PPMUMFC_L 3
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#define BIT_MFC_CLK_SMMUMFC_R 2
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#define BIT_MFC_CLK_SMMUMFC_L 1
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#define BIT_MFC_CLK_MFC 0
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#define CLK_GATE_IP_MFC_ALL_EN ((CLK_EN << BIT_MFC_CLK_PPMUMFC_R)\
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| (CLK_EN << BIT_MFC_CLK_PPMUMFC_L)\
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| (CLK_EN << BIT_MFC_CLK_SMMUMFC_R)\
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| (CLK_EN << BIT_MFC_CLK_SMMUMFC_L)\
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| (CLK_EN << BIT_MFC_CLK_MFC))
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#define CLK_GATE_IP_MFC_ALL_DIS ~CLK_GATE_IP_MFC_ALL_EN
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#define BIT_G3D_CLK_QEG3D 2
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#define BIT_G3D_CLK_PPMUG3D 1
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#define BIT_G3D_CLK_G3D 0
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#define CLK_GATE_IP_G3D_ALL_EN ((CLK_EN << BIT_G3D_CLK_QEG3D)\
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| (CLK_EN << BIT_G3D_CLK_PPMUG3D)\
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| (CLK_EN << BIT_G3D_CLK_G3D))
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#define CLK_GATE_IP_G3D_ALL_DIS ~CLK_GATE_IP_G3D_ALL_EN
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#define BIT_IMAGE_CLK_PPMUIMAGE 9
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#define BIT_IMAGE_CLK_QEMDMA 8
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#define BIT_IMAGE_CLK_QEROTATOR 7
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#define BIT_IMAGE_CLK_QEG2D 6
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#define BIT_IMAGE_CLK_SMMUMDMA 5
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#define BIT_IMAGE_CLK_SMMUROTATOR 4
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#define BIT_IMAGE_CLK_SMMUG2D 3
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#define BIT_IMAGE_CLK_MDMA 2
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#define BIT_IMAGE_CLK_ROTATOR 1
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#define BIT_IMAGE_CLK_G2D 0
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#define CLK_GATE_IP_IMAGE_ALL_EN ((CLK_EN << BIT_IMAGE_CLK_PPMUIMAGE)\
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| (CLK_EN << BIT_IMAGE_CLK_QEMDMA)\
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| (CLK_EN << BIT_IMAGE_CLK_QEROTATOR)\
|
|
| (CLK_EN << BIT_IMAGE_CLK_QEG2D)\
|
|
| (CLK_EN << BIT_IMAGE_CLK_SMMUMDMA)\
|
|
| (CLK_EN << BIT_IMAGE_CLK_SMMUROTATOR)\
|
|
| (CLK_EN << BIT_IMAGE_CLK_SMMUG2D)\
|
|
| (CLK_EN << BIT_IMAGE_CLK_MDMA)\
|
|
| (CLK_EN << BIT_IMAGE_CLK_ROTATOR)\
|
|
| (CLK_EN << BIT_IMAGE_CLK_G2D))
|
|
#define CLK_GATE_IP_IMAGE_ALL_DIS ~CLK_GATE_IP_IMAGE_ALL_EN
|
|
|
|
#define BIT_LCD0_CLK_PPMULCD0 5
|
|
#define BIT_LCD0_CLK_SMMUFIMD0 4
|
|
#define BIT_LCD0_CLK_DSIM0 3
|
|
#define BIT_LCD0_CLK_MDNIE0 2
|
|
#define BIT_LCD0_CLK_MIE0 1
|
|
#define BIT_LCD0_CLK_FIMD0 0
|
|
#define CLK_GATE_IP_LCD0_ALL_EN ((CLK_EN << BIT_LCD0_CLK_PPMULCD0)\
|
|
| (CLK_EN << BIT_LCD0_CLK_SMMUFIMD0)\
|
|
| (CLK_EN << BIT_LCD0_CLK_DSIM0)\
|
|
| (CLK_EN << BIT_LCD0_CLK_MDNIE0)\
|
|
| (CLK_EN << BIT_LCD0_CLK_MIE0)\
|
|
| (CLK_EN << BIT_LCD0_CLK_FIMD0))
|
|
#define CLK_GATE_IP_LCD0_ALL_DIS ~CLK_GATE_IP_LCD0_ALL_EN
|
|
|
|
#define BIT_LCD1_CLK_PPMULCD1 5
|
|
#define BIT_LCD1_CLK_SMMUFIMD1 4
|
|
#define BIT_LCD1_CLK_DSIM1 3
|
|
#define BIT_LCD1_CLK_MDNIE1 2
|
|
#define BIT_LCD1_CLK_MIE1 1
|
|
#define BIT_LCD1_CLK_FIMD1 0
|
|
#define CLK_GATE_IP_LCD1_ALL_EN ((CLK_EN << BIT_LCD1_CLK_PPMULCD1)\
|
|
| (CLK_EN << BIT_LCD1_CLK_SMMUFIMD1)\
|
|
| (CLK_EN << BIT_LCD1_CLK_DSIM1)\
|
|
| (CLK_EN << BIT_LCD1_CLK_MDNIE1)\
|
|
| (CLK_EN << BIT_LCD1_CLK_MIE1)\
|
|
| (CLK_EN << BIT_LCD1_CLK_FIMD1))
|
|
#define CLK_GATE_IP_LCD1_ALL_DIS ~CLK_GATE_IP_LCD1_ALL_EN
|
|
|
|
#define BIT_FSYS_CLK_SMMUPCIE 18
|
|
#define BIT_FSYS_CLK_PPMUFILE 17
|
|
#define BIT_FSYS_CLK_NFCON 16
|
|
#define BIT_FSYS_CLK_ONENAND 15
|
|
#define BIT_FSYS_CLK_PCIE 14
|
|
#define BIT_FSYS_CLK_USBDEVICE 13
|
|
#define BIT_FSYS_CLK_USBHOST 12
|
|
#define BIT_FSYS_CLK_SROMC 11
|
|
#define BIT_FSYS_CLK_SATA 10
|
|
#define BIT_FSYS_CLK_SDMMC4 9
|
|
#define BIT_FSYS_CLK_SDMMC3 8
|
|
#define BIT_FSYS_CLK_SDMMC2 7
|
|
#define BIT_FSYS_CLK_SDMMC1 6
|
|
#define BIT_FSYS_CLK_SDMMC0 5
|
|
#define BIT_FSYS_CLK_TSI 4
|
|
#define BIT_FSYS_CLK_SATAPHY 3
|
|
#define BIT_FSYS_CLK_PCIEPHY 2
|
|
#define BIT_FSYS_CLK_PDMA1 1
|
|
#define BIT_FSYS_CLK_PDMA0 0
|
|
#define CLK_GATE_IP_FSYS_ALL_EN ((CLK_EN << BIT_FSYS_CLK_SMMUPCIE)\
|
|
| (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
|
|
| (CLK_EN << BIT_FSYS_CLK_NFCON)\
|
|
| (CLK_EN << BIT_FSYS_CLK_ONENAND)\
|
|
| (CLK_EN << BIT_FSYS_CLK_PCIE)\
|
|
| (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
|
|
| (CLK_EN << BIT_FSYS_CLK_USBHOST)\
|
|
| (CLK_EN << BIT_FSYS_CLK_SROMC)\
|
|
| (CLK_EN << BIT_FSYS_CLK_SATA)\
|
|
| (CLK_EN << BIT_FSYS_CLK_SDMMC4)\
|
|
| (CLK_EN << BIT_FSYS_CLK_SDMMC3)\
|
|
| (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
|
|
| (CLK_EN << BIT_FSYS_CLK_SDMMC1)\
|
|
| (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
|
|
| (CLK_EN << BIT_FSYS_CLK_TSI)\
|
|
| (CLK_EN << BIT_FSYS_CLK_SATAPHY)\
|
|
| (CLK_EN << BIT_FSYS_CLK_PCIEPHY)\
|
|
| (CLK_EN << BIT_FSYS_CLK_PDMA1)\
|
|
| (CLK_EN << BIT_FSYS_CLK_PDMA0))
|
|
#define CLK_GATE_IP_FSYS_ALL_DIS ~CLK_GATE_IP_FSYS_ALL_EN
|
|
|
|
#define BIT_GPS_CLK_SMMUGPS 1
|
|
#define BIT_GPS_CLK_GPS 0
|
|
#define CLK_GATE_IP_GPS_ALL_EN ((CLK_EN << BIT_GPS_CLK_SMMUGPS)\
|
|
| (CLK_EN << BIT_GPS_CLK_GPS))
|
|
#define CLK_GATE_IP_GPS_ALL_DIS ~CLK_GATE_IP_GPS_ALL_EN
|
|
|
|
#define BIT_PERIL_CLK_MODEMIF 28
|
|
#define BIT_PERIL_CLK_AC97 27
|
|
#define BIT_PERIL_CLK_SPDIF 26
|
|
#define BIT_PERIL_CLK_SLIMBUS 25
|
|
#define BIT_PERIL_CLK_PWM 24
|
|
#define BIT_PERIL_CLK_PCM2 23
|
|
#define BIT_PERIL_CLK_PCM1 22
|
|
#define BIT_PERIL_CLK_I2S2 21
|
|
#define BIT_PERIL_CLK_I2S1 20
|
|
#define BIT_PERIL_CLK_RESERVED0 19
|
|
#define BIT_PERIL_CLK_SPI2 18
|
|
#define BIT_PERIL_CLK_SPI1 17
|
|
#define BIT_PERIL_CLK_SPI0 16
|
|
#define BIT_PERIL_CLK_TSADC 15
|
|
#define BIT_PERIL_CLK_I2CHDMI 14
|
|
#define BIT_PERIL_CLK_I2C7 13
|
|
#define BIT_PERIL_CLK_I2C6 12
|
|
#define BIT_PERIL_CLK_I2C5 11
|
|
#define BIT_PERIL_CLK_I2C4 10
|
|
#define BIT_PERIL_CLK_I2C3 9
|
|
#define BIT_PERIL_CLK_I2C2 8
|
|
#define BIT_PERIL_CLK_I2C1 7
|
|
#define BIT_PERIL_CLK_I2C0 6
|
|
#define BIT_PERIL_CLK_RESERVED1 5
|
|
#define BIT_PERIL_CLK_UART4 4
|
|
#define BIT_PERIL_CLK_UART3 3
|
|
#define BIT_PERIL_CLK_UART2 2
|
|
#define BIT_PERIL_CLK_UART1 1
|
|
#define BIT_PERIL_CLK_UART0 0
|
|
#define CLK_GATE_IP_PERIL_ALL_EN ((CLK_EN << BIT_PERIL_CLK_MODEMIF)\
|
|
| (CLK_EN << BIT_PERIL_CLK_AC97)\
|
|
| (CLK_EN << BIT_PERIL_CLK_SPDIF)\
|
|
| (CLK_EN << BIT_PERIL_CLK_SLIMBUS)\
|
|
| (CLK_EN << BIT_PERIL_CLK_PWM)\
|
|
| (CLK_EN << BIT_PERIL_CLK_PCM2)\
|
|
| (CLK_EN << BIT_PERIL_CLK_PCM1)\
|
|
| (CLK_EN << BIT_PERIL_CLK_I2S2)\
|
|
| (CLK_EN << BIT_PERIL_CLK_I2S1)\
|
|
| (CLK_EN << BIT_PERIL_CLK_RESERVED0)\
|
|
| (CLK_EN << BIT_PERIL_CLK_SPI2)\
|
|
| (CLK_EN << BIT_PERIL_CLK_SPI1)\
|
|
| (CLK_EN << BIT_PERIL_CLK_SPI0)\
|
|
| (CLK_EN << BIT_PERIL_CLK_TSADC)\
|
|
| (CLK_EN << BIT_PERIL_CLK_I2CHDMI)\
|
|
| (CLK_EN << BIT_PERIL_CLK_I2C7)\
|
|
| (CLK_EN << BIT_PERIL_CLK_I2C6)\
|
|
| (CLK_EN << BIT_PERIL_CLK_I2C5)\
|
|
| (CLK_EN << BIT_PERIL_CLK_I2C4)\
|
|
| (CLK_EN << BIT_PERIL_CLK_I2C3)\
|
|
| (CLK_EN << BIT_PERIL_CLK_I2C2)\
|
|
| (CLK_EN << BIT_PERIL_CLK_I2C1)\
|
|
| (CLK_EN << BIT_PERIL_CLK_I2C0)\
|
|
| (CLK_EN << BIT_PERIL_CLK_RESERVED1)\
|
|
| (CLK_EN << BIT_PERIL_CLK_UART4)\
|
|
| (CLK_EN << BIT_PERIL_CLK_UART3)\
|
|
| (CLK_EN << BIT_PERIL_CLK_UART2)\
|
|
| (CLK_EN << BIT_PERIL_CLK_UART1)\
|
|
| (CLK_EN << BIT_PERIL_CLK_UART0))
|
|
#define CLK_GATE_IP_PERIL_ALL_DIS ~CLK_GATE_IP_PERIL_ALL_EN
|
|
|
|
#define BIT_PERIR_CLK_TMU_APBIF 17
|
|
#define BIT_PERIR_CLK_KEYIF 16
|
|
#define BIT_PERIR_CLK_RTC 15
|
|
#define BIT_PERIR_CLK_WDT 14
|
|
#define BIT_PERIR_CLK_MCT 13
|
|
#define BIT_PERIR_CLK_SECKEY 12
|
|
#define BIT_PERIR_CLK_HDMI_CEC 11
|
|
#define BIT_PERIR_CLK_TZPC5 10
|
|
#define BIT_PERIR_CLK_TZPC4 9
|
|
#define BIT_PERIR_CLK_TZPC3 8
|
|
#define BIT_PERIR_CLK_TZPC2 7
|
|
#define BIT_PERIR_CLK_TZPC1 6
|
|
#define BIT_PERIR_CLK_TZPC0 5
|
|
#define BIT_PERIR_CLK_CMU_DMCPART 4
|
|
#define BIT_PERIR_CLK_RESERVED 3
|
|
#define BIT_PERIR_CLK_CMU_APBIF 2
|
|
#define BIT_PERIR_CLK_SYSREG 1
|
|
#define BIT_PERIR_CLK_CHIP_ID 0
|
|
#define CLK_GATE_IP_PERIR_ALL_EN ((CLK_EN << BIT_PERIR_CLK_TMU_APBIF)\
|
|
| (CLK_EN << BIT_PERIR_CLK_KEYIF)\
|
|
| (CLK_EN << BIT_PERIR_CLK_RTC)\
|
|
| (CLK_EN << BIT_PERIR_CLK_WDT)\
|
|
| (CLK_EN << BIT_PERIR_CLK_MCT)\
|
|
| (CLK_EN << BIT_PERIR_CLK_SECKEY)\
|
|
| (CLK_EN << BIT_PERIR_CLK_HDMI_CEC)\
|
|
| (CLK_EN << BIT_PERIR_CLK_TZPC5)\
|
|
| (CLK_EN << BIT_PERIR_CLK_TZPC4)\
|
|
| (CLK_EN << BIT_PERIR_CLK_TZPC3)\
|
|
| (CLK_EN << BIT_PERIR_CLK_TZPC2)\
|
|
| (CLK_EN << BIT_PERIR_CLK_TZPC1)\
|
|
| (CLK_EN << BIT_PERIR_CLK_TZPC0)\
|
|
| (CLK_EN << BIT_PERIR_CLK_CMU_DMCPART)\
|
|
| (CLK_EN << BIT_PERIR_CLK_RESERVED)\
|
|
| (CLK_EN << BIT_PERIR_CLK_CMU_APBIF)\
|
|
| (CLK_EN << BIT_PERIR_CLK_SYSREG)\
|
|
| (CLK_EN << BIT_PERIR_CLK_CHIP_ID))
|
|
#define CLK_GATE_IP_PERIR_ALL_DIS ~CLK_GATE_IP_PERIR_ALL_EN
|
|
|
|
#define BIT_BLOCK_CLK_GPS 7
|
|
#define BIT_BLOCK_CLK_RESERVED 6
|
|
#define BIT_BLOCK_CLK_LCD1 5
|
|
#define BIT_BLOCK_CLK_LCD0 4
|
|
#define BIT_BLOCK_CLK_G3D 3
|
|
#define BIT_BLOCK_CLK_MFC 2
|
|
#define BIT_BLOCK_CLK_TV 1
|
|
#define BIT_BLOCK_CLK_CAM 0
|
|
#define CLK_GATE_BLOCK_ALL_EN ((CLK_EN << BIT_BLOCK_CLK_GPS)\
|
|
| (CLK_EN << BIT_BLOCK_CLK_RESERVED)\
|
|
| (CLK_EN << BIT_BLOCK_CLK_LCD1)\
|
|
| (CLK_EN << BIT_BLOCK_CLK_LCD0)\
|
|
| (CLK_EN << BIT_BLOCK_CLK_G3D)\
|
|
| (CLK_EN << BIT_BLOCK_CLK_MFC)\
|
|
| (CLK_EN << BIT_BLOCK_CLK_TV)\
|
|
| (CLK_EN << BIT_BLOCK_CLK_CAM))
|
|
#define CLK_GATE_BLOCK_ALL_DIS ~CLK_GATE_BLOCK_ALL_EN
|
|
|
|
/*
|
|
* GATE CAM : All block
|
|
* GATE VP : All block
|
|
* GATE MFC : All block
|
|
* GATE G3D : All block
|
|
* GATE IMAGE : All block
|
|
* GATE LCD0 : All block
|
|
* GATE LCD1 : All block
|
|
* GATE FSYS : Enable - PDMA0,1, SDMMC0,2, USBHOST, USBDEVICE, PPMUFILE
|
|
* GATE GPS : All block
|
|
* GATE PERI Left : All Enable, Block - SLIMBUS, SPDIF, AC97
|
|
* GATE PERI Right : All Enable, Block - KEYIF
|
|
* GATE Block : All block
|
|
*/
|
|
#define CLK_GATE_IP_CAM_VAL CLK_GATE_IP_CAM_ALL_DIS
|
|
#define CLK_GATE_IP_VP_VAL CLK_GATE_IP_VP_ALL_DIS
|
|
#define CLK_GATE_IP_MFC_VAL CLK_GATE_IP_MFC_ALL_DIS
|
|
#define CLK_GATE_IP_G3D_VAL CLK_GATE_IP_G3D_ALL_DIS
|
|
#define CLK_GATE_IP_IMAGE_VAL CLK_GATE_IP_IMAGE_ALL_DIS
|
|
#define CLK_GATE_IP_LCD0_VAL CLK_GATE_IP_LCD0_ALL_DIS
|
|
#define CLK_GATE_IP_LCD1_VAL CLK_GATE_IP_LCD1_ALL_DIS
|
|
#define CLK_GATE_IP_FSYS_VAL (CLK_GATE_IP_FSYS_ALL_DIS \
|
|
| (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
|
|
| (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
|
|
| (CLK_EN << BIT_FSYS_CLK_USBHOST)\
|
|
| (CLK_EN << BIT_FSYS_CLK_SROMC)\
|
|
| (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
|
|
| (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
|
|
| (CLK_EN << BIT_FSYS_CLK_PDMA1)\
|
|
| (CLK_EN << BIT_FSYS_CLK_PDMA0))
|
|
#define CLK_GATE_IP_GPS_VAL CLK_GATE_IP_GPS_ALL_DIS
|
|
#define CLK_GATE_IP_PERIL_VAL (CLK_GATE_IP_PERIL_ALL_DIS \
|
|
| ~((CLK_EN << BIT_PERIL_CLK_AC97)\
|
|
| (CLK_EN << BIT_PERIL_CLK_SPDIF)\
|
|
| (CLK_EN << BIT_PERIL_CLK_I2C2)\
|
|
| (CLK_EN << BIT_PERIL_CLK_SLIMBUS)))
|
|
#define CLK_GATE_IP_PERIR_VAL (CLK_GATE_IP_PERIR_ALL_DIS \
|
|
| ~((CLK_EN << BIT_PERIR_CLK_KEYIF)))
|
|
#define CLK_GATE_BLOCK_VAL CLK_GATE_BLOCK_ALL_DIS
|
|
|
|
/* PS_HOLD: Data Hight, Output En */
|
|
#define BIT_DAT 8
|
|
#define BIT_EN 9
|
|
#define EXYNOS4_PS_HOLD_CON_VAL (0x1 << BIT_DAT | 0x1 << BIT_EN)
|
|
|
|
#endif
|