mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
70 lines
1.6 KiB
C
70 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2008-2009 Samsung Electronics
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* Kyungmin Park <kyungmin.park@samsung.com>
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*/
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#include <common.h>
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#include <linux/compat.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/onenand.h>
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#include <linux/mtd/samsung_onenand.h>
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#include <onenand_uboot.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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int onenand_board_init(struct mtd_info *mtd)
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{
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struct onenand_chip *this = mtd->priv;
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struct s5pc100_clock *clk =
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(struct s5pc100_clock *)samsung_get_base_clock();
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struct samsung_onenand *onenand;
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int value;
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this->base = (void *)S5PC100_ONENAND_BASE;
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onenand = (struct samsung_onenand *)this->base;
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/* D0 Domain memory clock gating */
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value = readl(&clk->gate_d01);
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value &= ~(1 << 2); /* CLK_ONENANDC */
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value |= (1 << 2);
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writel(value, &clk->gate_d01);
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value = readl(&clk->src0);
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value &= ~(1 << 24); /* MUX_1nand: 0 from HCLKD0 */
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value &= ~(1 << 20); /* MUX_HREF: 0 from FIN_27M */
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writel(value, &clk->src0);
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value = readl(&clk->div1);
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value &= ~(3 << 16); /* PCLKD1_RATIO */
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value |= (1 << 16);
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writel(value, &clk->div1);
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writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset);
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while (!(readl(&onenand->int_err_stat) & RST_CMP))
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continue;
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writel(RST_CMP, &onenand->int_err_ack);
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/*
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* Access_Clock [2:0]
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* 166 MHz, 134 Mhz : 3
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* 100 Mhz, 60 Mhz : 2
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*/
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writel(0x3, &onenand->acc_clock);
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writel(INT_ERR_ALL, &onenand->int_err_mask);
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writel(1 << 0, &onenand->int_pin_en); /* Enable */
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value = readl(&onenand->int_err_mask);
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value &= ~RDY_ACT;
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writel(value, &onenand->int_err_mask);
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s3c_onenand_init(mtd);
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return 0;
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}
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