mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
183 lines
7.0 KiB
C
183 lines
7.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Stout board CPLD definition
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*
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* Copyright (C) 2015 Renesas Electronics Europe GmbH
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* Copyright (C) 2015 Renesas Electronics Corporation
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* Copyright (C) 2015 Cogent Embedded, Inc.
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*/
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#ifndef _CPLD_H_
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#define _CPLD_H_
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/* power-up behaviour */
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#define MODE_MSK_FREE_RUN 0x00000001
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#define MODE_VAL_FREE_RUN 0x00000000
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#define MODE_MSK_STEP_UP 0x00000001
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#define MODE_VAL_STEP_UP 0x00000000
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/* boot source */
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#define MODE_MSK_BOOT_SQPI_16KB_FAST 0x0000000E
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#define MODE_VAL_BOOT_SQPI_16KB_FAST 0x00000004
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#define MODE_MSK_BOOT_SQPI_16KB_SLOW 0x0000000E
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#define MODE_VAL_BOOT_SQPI_16KB_SLOW 0x00000008
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#define MODE_MSK_BOOT_SQPI_4KB_SLOW 0x0000000E
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#define MODE_VAL_BOOT_SQPI_4KB_SLOW 0x0000000C
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/* booting CPU */
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#define MODE_MSK_BOOT_CA15 0x000000C0
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#define MODE_VAL_BOOT_CA15 0x00000000
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#define MODE_MSK_BOOT_CA7 0x000000C0
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#define MODE_VAL_BOOT_CA7 0x00000040
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#define MODE_MSK_BOOT_SH4 0x000000C0
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#define MODE_VAL_BOOT_SH4 0x000000C0
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/* JTAG connection */
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#define MODE_MSK_JTAG_CORESIGHT 0xC0301C00
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#define MODE_VAL_JTAG_CORESIGHT 0x00200000
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#define MODE_MSK_JTAG_SH4 0xC0301C00
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#define MODE_VAL_JTAG_SH4 0x00300000
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/* DDR3 (PLL) speed */
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#define MODE_MSK_DDR3_1600 0x00080000
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#define MODE_VAL_DDR3_1600 0x00000000
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#define MODE_MSK_DDR3_1333 0x00080000
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#define MODE_VAL_DDR3_1333 0x00080000
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/* ComboPhy0 mode */
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#define MODE_MSK_PHY0_SATA0 0x01000000
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#define MODE_VAL_PHY0_SATA0 0x00000000
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#define MODE_MSK_PHY0_PCIE 0x01000000
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#define MODE_VAL_PHY0_PCIE 0x01000000
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/* ComboPhy1 mode */
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#define MODE_MSK_PHY1_SATA1 0x00800000
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#define MODE_VAL_PHY1_SATA1 0x00000000
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#define MODE_MSK_PHY1_USB3 0x00800000
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#define MODE_VAL_PHY1_USB3 0x00800000
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/*
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* Illegal multiplexer combinations.
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* MUX Conflicts
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* name with any one of
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* VIN0_BT656 VIN0_full, SD2
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* VIN0_full VIN0_BT656, SD2, AVB, VIN2_(all)
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* VIN1_BT656 VIN1_(others), SD0
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* VIN1_10bit VIN1_(others), SD0, VIN3_with*, I2C1
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* VIN1_12bit VIN1_(others), SD0, VIN3_with*, I2C1, SCIFA0_(all)
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* VIN2_BT656 VIN0_full, VIN2_(others), AVB,
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* VIN2_withSYNC VIN0_full, VIN2_(others), AVB, I2C1, SCIFA0_(all),
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* VIN3_with*
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* VIN2_withFIELD VIN0_full, VIN2_(others), AVB, SQPI_(all)
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* VIN2_withSYNCandFIELD VIN0_full, VIN2_(others), AVB, SQPI_(all), I2C1,
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* SCIFA0_(all), VIN3_with*
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* VIN3_BT656 VIN3_(others), IRQ3
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* VIN3_withFIELD VIN3_(others), IRQ3, VIN1_12bit, VIN2_withSYNC,
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* VIN2_withSYNCandFIELD, VIN1_10bit
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* VIN3_withSYNCandFIELD VIN3_(others), IRQ3, VIN1_12bit, VIN2_withSYNC,
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* VIN2_withSYNCandFIELD, VIN1_10bit, I2C1
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* AVB VIN0_full, VIN2_(all)
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* QSPI_ONBOARD VIN2_withFIELD, VIN2_withSYNCandFIELD, QSPI_COMEXPRESS
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* QSPI_COMEXPRESS VIN2_withFIELD, VIN2_withSYNCandFIELD, QSPI_ONBOARD
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* I2C1 VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD,
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* VIN3_withSYNCandFIELD
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* IRQ3 VIN3_(all)
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* SCIFA0_USB VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD,
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* SCIFA0_COMEXPRESS
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* SCIFA0_COMEXPRESS VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD,
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* SCIFA0_USB
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* SCIFA2 PWM210
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* ETH_ONBOARD ETH_COMEXPRESS
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* ETH_COMEXPRESS ETH_ONBOARD
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* SD0 VIN1_(all)
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* SD2 VIN0_(all)
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* PWM210 SCIFA2
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*/
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/* connected to COM Express connector and CN6 for camera, BT656 only */
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#define MUX_MSK_VIN0_BT656 0x00001001
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#define MUX_VAL_VIN0_BT656 0x00000000
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/* connected to COM Express connector and CN6 for camera, all modes */
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#define MUX_MSK_VIN0_full 0x00001007
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#define MUX_VAL_VIN0_full 0x00000002
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/* connected to COM Express connector, BT656 only */
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#define MUX_MSK_VIN1_BT656 0x00000801
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#define MUX_VAL_VIN1_BT656 0x00000800
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/* connected to COM Express connector, all 10-bit modes */
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#define MUX_MSK_VIN1_10bit 0x00000821
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#define MUX_VAL_VIN1_10bit 0x00000800
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/* connected to COM Express connector, all 12-bit modes */
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#define MUX_MSK_VIN1_12bit 0x000008A1
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#define MUX_VAL_VIN1_12bit 0x00000880
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/* connected to COM Express connector, BT656 only */
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#define MUX_MSK_VIN2_BT656 0x00000007
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#define MUX_VAL_VIN2_BT656 0x00000006
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/* connected to COM Express connector, modes with sync signals */
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#define MUX_MSK_VIN2_withSYNC 0x000000A7
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#define MUX_VAL_VIN2_withSYNC 0x00000086
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/* connected to COM Express connector, modes with field, clken signals */
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#define MUX_MSK_VIN2_withFIELD 0x0000000F
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#define MUX_VAL_VIN2_withFIELD 0x0000000E
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/* connected to COM Express connector, modes with sync, field, clken signals */
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#define MUX_MSK_VIN2_withSYNCandFIELD 0x000000AF
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#define MUX_VAL_VIN2_withSYNCandFIELD 0x0000008E
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/* connected to COM Express connector, BT656 only */
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#define MUX_MSK_VIN3_BT656 0x00000101
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#define MUX_VAL_VIN3_BT656 0x00000100
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/* connected to COM Express connector, modes with field, clken signals */
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#define MUX_MSK_VIN3_withFIELD 0x00000121
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#define MUX_VAL_VIN3_withFIELD 0x00000120
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/* connected to COM Express connector, modes with sync, field, clken signals */
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#define MUX_MSK_VIN3_withSYNCandFIELD 0x00000161
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#define MUX_VAL_VIN3_withSYNCandFIELD 0x00000120
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/* connected to COM Express connector (RGMII) */
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#define MUX_MSK_AVB 0x00000003
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#define MUX_VAL_AVB 0x00000000
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/* connected to on-board QSPI flash */
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#define MUX_MSK_QSPI_ONBOARD 0x00000019
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#define MUX_VAL_QSPI_ONBOARD 0x00000000
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/* connected to COM Express connector */
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#define MUX_MSK_QSPI_COMEXPRESS 0x00000019
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#define MUX_VAL_QSPI_COMEXPRESS 0x00000010
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/* connected to COM Express connector and PMIC */
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#define MUX_MSK_I2C1 0x00000061
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#define MUX_VAL_I2C1 0x00000060
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/* connected to HDMI driver */
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#define MUX_MSK_IRQ3 0x00000101
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#define MUX_VAL_IRQ3 0x00000000
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/* connected to USB/FTDI */
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#define MUX_MSK_SCIFA0_USB 0x00004081
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#define MUX_VAL_SCIFA0_USB 0x00004000
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/* connected to COM Express connector */
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#define MUX_MSK_SCIFA0_COMEXPRESS 0x00004081
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#define MUX_VAL_SCIFA0_COMEXPRESS 0x00000000
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/* connected to COM Express connector */
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#define MUX_MSK_SCIFA2 0x00002001
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#define MUX_VAL_SCIFA2 0x00000000
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/* connected to on-board 10/100 Phy */
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#define MUX_MSK_ETH_ONBOARD 0x00000600
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#define MUX_VAL_ETH_ONBOARD 0x00000000
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/* connected to COM Express connector (RMII) */
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#define MUX_MSK_ETH_COMEXPRESS 0x00000600
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#define MUX_VAL_ETH_COMEXPRESS 0x00000400
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/* connected to on-board MicroSD slot */
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#define MUX_MSK_SD0 0x00000801
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#define MUX_VAL_SD0 0x00000000
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/* connected to COM Express connector */
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#define MUX_MSK_SD2 0x00001001
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#define MUX_VAL_SD2 0x00001000
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/* connected to COM Express connector */
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#define MUX_MSK_PWM210 0x00002001
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#define MUX_VAL_PWM210 0x00002000
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#define HDMI_MSK 0x07
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#define HDMI_OFF 0x00
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#define HDMI_ONBOARD 0x07
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#define HDMI_COMEXPRESS 0x05
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#define HDMI_ONBOARD_NODDC 0x03
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#define HDMI_COMEXPRESS_NODDC 0x01
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void cpld_init(void);
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#endif /* _CPLD_H_ */
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