mirror of
https://github.com/brain-hackers/u-boot-brain
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4eeb9fe847
Currently PCA9450 might have address 0x25 or 0x35, so let user choose the address. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
131 lines
2.7 KiB
C
131 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2020 PHYTEC Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <hang.h>
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#include <init.h>
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#include <log.h>
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#include <power/pmic.h>
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#include <power/pca9450.h>
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#include <spl.h>
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DECLARE_GLOBAL_DATA_PTR;
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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return BOOT_DEVICE_BOOTROM;
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}
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void spl_dram_init(void)
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{
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ddr_init(&dram_timing);
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}
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#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
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.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
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.gp = IMX_GPIO_NR(5, 14),
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},
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.sda = {
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.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
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.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
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.gp = IMX_GPIO_NR(5, 15),
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},
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};
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int power_init_board(void)
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{
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struct pmic *p;
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int ret;
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ret = power_pca9450_init(0, 0x25);
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if (ret)
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printf("power init failed");
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p = pmic_get("PCA9450");
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pmic_probe(p);
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/* BUCKxOUT_DVS0/1 control BUCK123 output */
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pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
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/* increase VDD_SOC to typical value 0.95V */
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pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
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/* set WDOG_B_CFG to cold reset */
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pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
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return 0;
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}
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int board_fit_config_name_match(const char *name)
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{
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return 0;
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}
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#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
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#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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static iomux_v3_cfg_t const uart_pads[] = {
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MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const wdog_pads[] = {
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MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
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};
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int board_early_init_f(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
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set_wdog_reset(wdog);
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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int ret;
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arch_cpu_init();
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init_uart_clk(1);
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board_early_init_f();
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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preloader_console_init();
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enable_tzc380();
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
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power_init_board();
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/* DDR initialization */
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spl_dram_init();
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}
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