89 lines
1.7 KiB
C
89 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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// Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua>
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#include <asm/arch-mx6/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <common.h>
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#include <env.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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int board_early_init_f(void)
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{
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return 0;
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}
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static int setup_fec_clock(void)
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{
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if (IS_ENABLED(CONFIG_FEC_MXC) && !IS_ENABLED(CONFIG_CLK_IMX6Q)) {
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struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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int ret;
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/*
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* Use 50M anatop loopback REF_CLK1 for ENET1,
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* clear gpr1[13], set gpr1[17].
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*/
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
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IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
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ret = enable_fec_anatop_clock(0, ENET_50MHZ);
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if (ret)
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return ret;
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if (!IS_ENABLED(CONFIG_EV_IMX280_NANO_X_MB)) {
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/*
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* Use 50M anatop loopback REF_CLK2 for ENET2,
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* clear gpr1[14], set gpr1[18].
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*/
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
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IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
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ret = enable_fec_anatop_clock(1, ENET_50MHZ);
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if (ret)
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return ret;
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}
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enable_enet_clk(1);
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}
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return 0;
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}
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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return setup_fec_clock();
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}
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int board_late_init(void)
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{
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if (IS_ENABLED(CONFIG_CMD_BMODE))
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add_board_boot_modes(NULL);
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if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
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const char *model;
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model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
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if (model)
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env_set("board_name", model);
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}
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if (is_boot_from_usb()) {
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env_set("bootcmd", "run bootcmd_mfg");
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env_set("bootdelay", "0");
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}
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return 0;
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}
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