56 lines
1.3 KiB
C
56 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* LS1028A TF-A calling support
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*
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* Copyright (c) 2020 Michael Walle <michael@walle.cc>
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*/
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#include <common.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <atf_common.h>
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#include <spl.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct region_info {
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u64 addr;
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u64 size;
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};
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struct dram_regions_info {
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u64 num_dram_regions;
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u64 total_dram_size;
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struct region_info region[CONFIG_NR_DRAM_BANKS];
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};
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struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry,
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uintptr_t bl33_entry,
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uintptr_t fdt_addr)
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{
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static struct dram_regions_info dram_regions_info = { 0 };
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struct bl_params *bl_params;
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struct bl_params_node *node;
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void *dcfg_ccsr = (void *)DCFG_BASE;
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int i;
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dram_regions_info.num_dram_regions = CONFIG_NR_DRAM_BANKS;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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dram_regions_info.region[i].addr = gd->bd->bi_dram[i].start;
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dram_regions_info.region[i].size = gd->bd->bi_dram[i].size;
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dram_regions_info.total_dram_size += gd->bd->bi_dram[i].size;
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}
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bl_params = bl2_plat_get_bl31_params_v2_default(bl32_entry, bl33_entry,
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fdt_addr);
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for_each_bl_params_node(bl_params, node) {
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if (node->image_id == ATF_BL31_IMAGE_ID) {
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node->ep_info->args.arg3 = (uintptr_t)&dram_regions_info;
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node->ep_info->args.arg4 = in_le32(dcfg_ccsr + DCFG_PORSR1);
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}
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}
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return bl_params;
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}
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