71 lines
1.6 KiB
C
71 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include <common.h>
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#include <asm/io.h>
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#include <asm/spl.h>
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#include <asm/arch-fsl-layerscape/fsl_serdes.h>
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#include <asm/arch-fsl-layerscape/soc.h>
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#define DCFG_RCWSR25 0x160
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#define GPINFO_HW_VARIANT_MASK 0xff
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#define SERDES_LNDGCR0 0x1ea08c0
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#define LNDGCR0_PROTS_MASK GENMASK(11, 7)
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#define LNDGCR0_PROTS_SATA (0x2 << 7)
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#define SERDES_LNDGCR1 0x1ea08c4
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#define LNDGCR1_RDAT_INV BIT(31)
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/*
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* On this board the SMARC PCIe lane D might be switched to SATA mode. This
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* makes sense if this lane is connected to a Mini PCI slot and a mSATA card
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* is plugged in. In this case, the RX pair is swapped and we need to invert
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* the received data.
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*/
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static void fixup_sata_rx_polarity(void)
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{
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u32 prot = in_le32(SERDES_LNDGCR0) & LNDGCR0_PROTS_MASK;
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u32 tmp;
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if (prot == LNDGCR0_PROTS_SATA) {
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tmp = in_le32(SERDES_LNDGCR1);
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tmp |= LNDGCR1_RDAT_INV;
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out_le32(SERDES_LNDGCR1, tmp);
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}
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}
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int sl28_variant(void)
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{
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return in_le32(DCFG_BASE + DCFG_RCWSR25) & GPINFO_HW_VARIANT_MASK;
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}
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int board_fit_config_name_match(const char *name)
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{
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int variant = sl28_variant();
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switch (variant) {
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case 1:
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return strcmp(name, "fsl-ls1028a-kontron-sl28-var1");
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case 2:
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return strcmp(name, "fsl-ls1028a-kontron-sl28-var2");
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case 3:
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return strcmp(name, "fsl-ls1028a-kontron-sl28-var3");
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case 4:
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return strcmp(name, "fsl-ls1028a-kontron-sl28-var4");
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default:
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return strcmp(name, "fsl-ls1028a-kontron-sl28");
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}
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}
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void board_boot_order(u32 *spl_boot_list)
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{
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spl_boot_list[0] = BOOT_DEVICE_SPI;
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}
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int board_early_init_f(void)
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{
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fixup_sata_rx_polarity();
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fsl_lsch3_early_init_f();
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return 0;
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}
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