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https://github.com/brain-hackers/u-boot-brain
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37bfd9cb50
Add basic support for the Hitachi Power Grids kmcent2 board, based on the NXP QorIQ T1040 SoC. Signed-off-by: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com> Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Niel Fourie <lusus@denx.de> Cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> [Fixed blank line at EOF errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
89 lines
2.1 KiB
C
89 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Keymile AG
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* Rainer Boschung <rainer.boschung@keymile.com>
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*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*/
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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#include <asm/mpc85xx_gpio.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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#include <hwconfig.h>
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#include <i2c.h>
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#include <init.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define DQSn_POS(n) (3 - (((n) - 1) % 4)) * 8
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#define DQSn_START(n, start) ((start) << DQSn_POS(n))
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void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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if (ctrl_num > 1) {
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printf("Not supported controller number %d\n", ctrl_num);
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return;
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}
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/* 1/2 clk delay between wr command and data strobe */
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popts->write_data_delay = 4;
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/* clk lauched 1/2 applied cylcle after address command */
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popts->clk_adjust = 4;
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/* 1T timing: command/address held for only 1 cycle */
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popts->twot_en = 0;
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popts->threet_en = 0;
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/* optimize cpo for erratum A-009942 */
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popts->cpo_sample = 0x3b;
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/* we have only one module, half str should be OK */
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popts->half_strength_driver_enable = 1;
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/*
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* Write leveling override
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*/
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/* set for DDR3-1600 */
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xf;
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popts->wrlvl_start = 0x7;
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/* DQS write leveling start time according layout */
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popts->wrlvl_ctl_2 = (DQSn_START(1, 0x06) |
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DQSn_START(2, 0x06) |
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DQSn_START(3, 0x07) |
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DQSn_START(4, 0x07));
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popts->wrlvl_ctl_3 = (DQSn_START(5, 0x07) |
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DQSn_START(6, 0x08) |
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DQSn_START(7, 0x08) |
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DQSn_START(8, 0x08));
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/*
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* rtt and wtt_wr override
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*/
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popts->rtt_override = 0;
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/* Enable ZQ calibration */
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popts->zq_en = 1;
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/* DHC_EN =1, ODT = 75 Ohm */
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
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}
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int dram_init(void)
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{
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phys_size_t dram_size;
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puts("Initializing....using SPD\n");
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dram_size = fsl_ddr_sdram();
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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gd->ram_size = dram_size;
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return 0;
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}
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