mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
258 lines
9.2 KiB
INI
258 lines
9.2 KiB
INI
# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2012
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# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com
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# Norbert Mayer, Keymile AG, norbert.mayer@keymile.com
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# Deepak Patel, XENTECH Limited, deepak.patel@xentech.co.uk
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# Refer doc/README.kwbimage for more details about how-to configure
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# and create kirkwood boot image
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#
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# This configuration applies to COGE5 design (ARM-part)
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# Two 8-Bit devices are connected on the 16-Bit bus on the same
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# chip-select. The supported devices are
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# MT47H256M8EB-3IT:C
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# MT47H256M8EB-25EIT:C
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# Boot Media configurations
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BOOT_FROM spi # Boot from SPI flash
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DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
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# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
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# bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
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# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
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# bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5])
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# bit 19-16: 1, MPPSel4 NF_IO[6]
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# bit 23-20: 1, MPPSel5 NF_IO[7]
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# bit 27-24: 1, MPPSel6 SYSRST_O
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# bit 31-28: 0, MPPSel7 GPO[7]
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DATA 0xFFD10004 0x03303300 # MPP Control 1 Register
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# bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged
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# bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged
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# bit 12-8: 3, MPPSel10 UA0_TXD
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# bit 15-12: 3, MPPSel11 UA0_RXD
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# bit 19-16: 0, MPPSel12 not connected
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# bit 23-20: 3, MPPSel13 GPIO[14]
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# bit 27-24: 3, MPPSel14 GPIO[15]
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# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal)
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DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
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# bit 3-0: 0, MPPSel16 GPIO[16]
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# bit 7-4: 0, MPPSel17 not connected
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# bit 11-8: 1, MPPSel18 NF_IO[0]
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# bit 15-12: 1, MPPSel19 NF_IO[1]
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# bit 19-16: 0, MPPSel20 GPIO[20]
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# bit 23-20: 0, MPPSel21 GPIO[21]
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# bit 27-24: 0, MPPSel22 GPIO[22]
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# bit 31-28: 0, MPPSel23 GPIO[23]
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# MPP Control 3-6 Register untouched (MPP24-49)
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DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
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# bit 2-0: 3, Reserved
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# bit 5-3: 3, Reserved
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# bit 6: 0, Reserved
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# bit 7: 0, RGMII-pads voltage = 3.3V
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# bit 10-8: 3, Reserved
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# bit 13-11: 3, Reserved
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# bit 14: 0, Reserved
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# bit 15: 0, MPP RGMII-pads voltage = 3.3V
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# bit 31-16 0x1B1B, Reserved
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DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
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# bit 0-1: 2, Tag RAM RTC RAM0
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# bit 3-2: 1, Tag RAM WTC RAM0
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# bit 7-4: 6, Reserved
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# bit 9-8: 2, Valid RAM RTC RAM
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# bit 11-10: 1, Valid RAM WTC RAM
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# bit 13-12: 2, Dirty RAM RTC RAM
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# bit 15-14: 1, Dirty RAM WTC RAM
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# bit 17-16: 2, Data RAM RTC RAM0
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# bit 19-18: 1, Data RAM WTC RAM0
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# bit 21-20: 2, Data RAM RTC RAM1
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# bit 23-22: 1, Data RAM WTC RAM1
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# bit 25-24: 2, Data RAM RTC RAM2
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# bit 27-26: 1, Data RAM WTC RAM2
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# bit 29-28: 2, Data RAM RTC RAM3
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# bit 31-30: 1, Data RAM WTC RAM4
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DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
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# bit 15-0: ?, Reserved
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# bit 17-16: 2, ECC RAM RTC RAM0
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# bit 19-18: 1, ECC RAM WTC RAM0
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# bit 31-20: ?,Reserved
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# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
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# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
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# SDRAM initalization
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DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
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# bit 13-0: 0x4E0, DDR2 clks refresh rate
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# bit 14: 0, reserved
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# bit 15: 0, reserved
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# bit 16: 0, CPU to Dram Write buffer policy
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# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic
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# bit 19-18: 0, reserved
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# bit 23-20: 0, reserved
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# bit 24: 1, enable exit self refresh mode on DDR access
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# bit 25: 1, required
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# bit 29-26: 0, reserved
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# bit 31-30: 1, reserved
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DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
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# bit 3-0: 0, reserved
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# bit 4: 0, 2T mode =addr/cmd in same cycle
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# bit 5: 0, clk is driven during self refresh, we don't care for APX
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# bit 6: 0, use recommended falling edge of clk for addr/cmd
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# bit 7-11: 0, reserved
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# bit 12-13: 1, reserved, required 1
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# bit 14: 0, input buffer always powered up
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# bit 17-15: 0, reserved
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# bit 18: 1, cpu lock transaction enabled
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# bit 19: 0, reserved
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# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
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# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM
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# bit 30-28: 3, required
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# bit 31: 0, no additional STARTBURST delay
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DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1)
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# bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles
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# bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles
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# bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles
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# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles
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# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles
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# bit 20: 0, extended TRAS msb
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# bit 23-21: 0, reserved
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# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles
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# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
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DATA 0xFFD0140C 0x0000003E # DDR Timing (High)
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# bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles
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# bit 8-7: 0, TR2R
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# bit 10-9: 0, TR2W
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# bit 12-11: 0, TW2W
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# bit 31-13: 0, reserved
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DATA 0xFFD01410 0x00000000 # DDR Address Control
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# bit 1-0: 0, Cs0width=x8 (2 devices)
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# bit 3-2: 0, Cs0size=2Gb
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# bit 5-4: 0, Cs1width=nonexistent
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# bit 7-6: 0, Cs1size =nonexistent
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# bit 9-8: 0, Cs2width=nonexistent
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# bit 11-10: 0, Cs2size =nonexistent
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# bit 13-12: 0, Cs3width=nonexistent
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# bit 15-14: 0, Cs3size =nonexistent
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# bit 16: 0, Cs0AddrSel
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# bit 17: 0, Cs1AddrSel
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# bit 18: 0, Cs2AddrSel
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# bit 19: 0, Cs3AddrSel
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# bit 31-20: 0, required
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DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
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# bit 0: 0, OpenPage enabled
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# bit 31-1: 0, required
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DATA 0xFFD01418 0x00000000 # DDR Operation
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# bit 3-0: 0, DDR cmd
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# bit 31-4: 0, required
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DATA 0xFFD0141C 0x00000652 # DDR Mode
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# bit 2-0: 2, Burst Length = 4
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# bit 3: 0, Burst Type
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# bit 6-4: 5, CAS Latency = 5
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# bit 7: 0, Test mode
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# bit 8: 0, DLL Reset
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# bit 11-9: 3, Write recovery for auto-precharge must be 3
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# bit 12: 0, Active power down exit time, fast exit
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# bit 14-13: 0, reserved
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# bit 31-15: 0, reserved
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DATA 0xFFD01420 0x00000006 # DDR Extended Mode
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# bit 0: 0, DDR DLL enabled
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# bit 1: 1, DDR drive strenght reduced
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# bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0]
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# bit 5-3: 0, required
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# bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1]
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# bit 9-7: 0, required
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# bit 10: 0, differential DQS enabled
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# bit 11: 0, required
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# bit 12: 0, DDR output buffer enabled
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# bit 31-13: 0 required
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DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
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# bit 2-0: 7, required
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# bit 3: 1, MBUS Burst Chop disabled
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# bit 6-4: 7, required
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# bit 7: 0, reserved
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# bit 8: 1, add sample stage required for > 266Mhz
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# bit 9: 0, no half clock cycle addition to dataout
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# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
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# bit 11: 0, 1/4 clock cycle skew disabled for write mesh
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# bit 15-12:0xf, required
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# bit 31-16: 0, required
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DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
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# bit 3-0: 0, required
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# bit 7-4: 2, M_ODT assertion 2 cycles after read start command
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# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command
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# (ODT turn off delay 2,5 clk cycles)
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# bit 15-12: 4, internal ODT time based on bit 7-4
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# with the considered SDRAM internal delay
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# bit 19-16: 8, internal ODT de-assertion based on bit 11-8
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# with the considered SDRAM internal delay
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# bit 31-20: 0, required
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DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High
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# bit 3-0: 2, M_ODT assertion same as bit 11-8
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# bit 7-4: 5, M_ODT de-assertion same as bit 15-12
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# bit 11-8: 4, internal ODT assertion 2 cycles after write start command
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# with the considered SDRAM internal delay
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# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
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# with the considered SDRAM internal delay
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DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
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# bit 23-0: 0, reserved
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# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24]
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DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size
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# bit 0: 1, Window enabled
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# bit 1: 0, Write Protect disabled
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# bit 3-2: 0, CS0 hit selected
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# bit 23-4:ones, required
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# bit 31-24:0x1F, Size (i.e. 512MB)
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DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
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DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
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DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
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DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
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# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
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# bit 7-4: 0, ODT0Rd, MODT[1] not asserted
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# bit 11-8: 0, required
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# big 15-11: 0, required
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# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
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# bit 23-20: 0, ODT0Wr, MODT[1] not asserted
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# bit 27-24: 0, required
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# bit 31-28: 0, required
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DATA 0xFFD01498 0x00000004 # DDR ODT Control (High)
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# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above
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# bit 3-2: 1, ODT1 never active
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# bit 31-4: 0, required
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DATA 0xFFD0149C 0x0000E801 # CPU ODT Control
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# bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
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# bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
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# bit 9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr
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# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm
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# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm
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# bit 14: 1, STARTBURST ODT enabled
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# bit 15: 1, Use ODT Block
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DATA 0xFFD01480 0x00000001 # DDR Initialization Control
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# bit 0: 1, enable DDR init upon this register write
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# bit 31-1: 0, reserved
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# End of Header extension
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DATA 0x0 0x0
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