mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
162 lines
5.1 KiB
INI
162 lines
5.1 KiB
INI
# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2010
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# Heiko Schocher, DENX Software Engineering, hs@denx.de.
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# Refer doc/README.kwbimage for more details about how-to configure
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# and create kirkwood boot image
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#
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# Boot Media configurations
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BOOT_FROM spi # Boot from SPI flash
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DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
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# bit 3-0: MPPSel0 2, NF_IO[2]
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# bit 7-4: MPPSel1 2, NF_IO[3]
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# bit 12-8: MPPSel2 2, NF_IO[4]
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# bit 15-12: MPPSel3 2, NF_IO[5]
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# bit 19-16: MPPSel4 1, NF_IO[6]
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# bit 23-20: MPPSel5 1, NF_IO[7]
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# bit 27-24: MPPSel6 1, SYSRST_O
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# bit 31-28: MPPSel7 0, GPO[7]
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DATA 0xFFD10004 0x03303300
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DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
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# bit 3-0: MPPSel16 0, GPIO[16]
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# bit 7-4: MPPSel17 0, GPIO[17]
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# bit 12-8: MPPSel18 1, NF_IO[0]
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# bit 15-12: MPPSel19 1, NF_IO[1]
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# bit 19-16: MPPSel20 0, GPIO[20]
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# bit 23-20: MPPSel21 0, GPIO[21]
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# bit 27-24: MPPSel22 0, GPIO[22]
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# bit 31-28: MPPSel23 0, GPIO[23]
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DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
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DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
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DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
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# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
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# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
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#Dram initalization
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DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register
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# bit13-0: 0x400 (DDR2 clks refresh rate)
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# bit23-14: zero
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# bit24: 1= enable exit self refresh mode on DDR access
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# bit25: 1 required
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# bit29-26: zero
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# bit31-30: 01
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DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
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# bit 3-0: 0 reserved
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# bit 4: 0=addr/cmd in smame cycle
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# bit 5: 0=clk is driven during self refresh, we don't care for APX
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# bit 6: 0=use recommended falling edge of clk for addr/cmd
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# bit14: 0=input buffer always powered up
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# bit18: 1=cpu lock transaction enabled
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# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
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# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
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# bit30-28: 3 required
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# bit31: 0=no additional STARTBURST delay
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DATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1)
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# bit3-0: TRAS lsbs
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# bit7-4: TRCD
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# bit11- 8: TRP
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# bit15-12: TWR
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# bit19-16: TWTR
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# bit20: TRAS msb
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# bit23-21: 0x0
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# bit27-24: TRRD
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# bit31-28: TRTP
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DATA 0xFFD0140C 0x00000033 # DDR Timing (High)
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# bit6-0: TRFC
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# bit8-7: TR2R
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# bit10-9: TR2W
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# bit12-11: TW2W
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# bit31-13: zero required
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DATA 0xFFD01410 0x0000000D # DDR Address Control
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# bit1-0: 01, Cs0width=x16
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# bit3-2: 11, Cs0size=1Gb
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# bit5-4: 00, Cs2width=nonexistent
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# bit7-6: 00, Cs1size =nonexistent
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# bit9-8: 00, Cs2width=nonexistent
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# bit11-10: 00, Cs2size =nonexistent
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# bit13-12: 00, Cs3width=nonexistent
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# bit15-14: 00, Cs3size =nonexistent
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# bit16: 0, Cs0AddrSel
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# bit17: 0, Cs1AddrSel
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# bit18: 0, Cs2AddrSel
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# bit19: 0, Cs3AddrSel
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# bit31-20: 0 required
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DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
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# bit0: 0, OpenPage enabled
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# bit31-1: 0 required
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DATA 0xFFD01418 0x00000000 # DDR Operation
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# bit3-0: 0x0, DDR cmd
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# bit31-4: 0 required
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DATA 0xFFD0141C 0x00000652 # DDR Mode
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DATA 0xFFD01420 0x00000044 # DDR Extended Mode
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# bit0: 0, DDR DLL enabled
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# bit1: 0, DDR drive strenght normal
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# bit2: 1, DDR ODT control lsd disabled
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# bit5-3: 000, required
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# bit6: 1, DDR ODT control msb, enabled
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# bit9-7: 000, required
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# bit10: 0, differential DQS enabled
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# bit11: 0, required
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# bit12: 0, DDR output buffer enabled
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# bit31-13: 0 required
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DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
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# bit2-0: 111, required
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# bit3 : 1 , MBUS Burst Chop disabled
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# bit6-4: 111, required
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# bit7 : 0
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# bit8 : 0 , no sample stage
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# bit9 : 0 , no half clock cycle addition to dataout
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# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
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# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
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# bit15-12: 1111 required
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# bit31-16: 0 required
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DATA 0xFFD01428 0x00074510
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DATA 0xFFD0147c 0x00007451
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DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
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DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
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# bit0: 1, Window enabled
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# bit1: 0, Write Protect disabled
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# bit3-2: 00, CS0 hit selected
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# bit23-4: ones, required
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# bit31-24: 0x07, Size (i.e. 128MB)
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DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
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DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
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DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
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DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low)
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# bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
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# bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
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DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
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# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
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# bit3-2: 00, ODT1 controlled by register
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# bit31-4: zero, required
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DATA 0xFFD0149C 0x0000FC11 # CPU ODT Control
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# bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
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# bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
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# bit9-8: 1, ODTEn, never active
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# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
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DATA 0xFFD01480 0x00000001 # DDR Initialization Control
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# bit0=1, enable DDR init upon this register write
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# End of Header extension
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DATA 0x0 0x0
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