mirror of
https://github.com/brain-hackers/u-boot-brain
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401d1c4f5d
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
233 lines
6.1 KiB
C
233 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* K+P iMX6Q KP_IMX6Q_TPC board configuration
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*
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* Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
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*/
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#include <common.h>
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#include <init.h>
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#include <log.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <spl.h>
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#include <linux/delay.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0x00C03F3F, &ccm->CCGR0);
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writel(0x0030FC03, &ccm->CCGR1);
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writel(0x0FFFC000, &ccm->CCGR2);
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writel(0x3FF00000, &ccm->CCGR3);
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writel(0x00FFF300, &ccm->CCGR4);
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writel(0x0F0000C3, &ccm->CCGR5);
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writel(0x000003FF, &ccm->CCGR6);
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}
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/* DDR3 */
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static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_sdclk_0 = 0x00000030,
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.dram_sdclk_1 = 0x00000030,
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.dram_cas = 0x00000030,
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.dram_ras = 0x00000030,
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.dram_reset = 0x00000030,
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = 0x00000030,
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.dram_sdodt1 = 0x00000030,
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.dram_sdqs0 = 0x00000018,
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.dram_sdqs1 = 0x00000018,
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.dram_sdqs2 = 0x00000018,
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.dram_sdqs3 = 0x00000018,
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.dram_sdqs4 = 0x00000018,
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.dram_sdqs5 = 0x00000018,
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.dram_sdqs6 = 0x00000018,
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.dram_sdqs7 = 0x00000018,
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.dram_dqm0 = 0x00000018,
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.dram_dqm1 = 0x00000018,
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.dram_dqm2 = 0x00000018,
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.dram_dqm3 = 0x00000018,
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.dram_dqm4 = 0x00000018,
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.dram_dqm5 = 0x00000018,
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.dram_dqm6 = 0x00000018,
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.dram_dqm7 = 0x00000018,
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};
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static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = 0x00000030,
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.grp_ctlds = 0x00000030,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = 0x00000018,
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.grp_b1ds = 0x00000018,
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.grp_b2ds = 0x00000018,
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.grp_b3ds = 0x00000018,
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.grp_b4ds = 0x00000018,
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.grp_b5ds = 0x00000018,
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.grp_b6ds = 0x00000018,
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.grp_b7ds = 0x00000018,
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};
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static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
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.p0_mpwldectrl0 = 0x001F001F,
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.p0_mpwldectrl1 = 0x001F001F,
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.p1_mpwldectrl0 = 0x001F001F,
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.p1_mpwldectrl1 = 0x001F001F,
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.p0_mpdgctrl0 = 0x43270338,
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.p0_mpdgctrl1 = 0x03200314,
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.p1_mpdgctrl0 = 0x431A032F,
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.p1_mpdgctrl1 = 0x03200263,
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.p0_mprddlctl = 0x4B434748,
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.p1_mprddlctl = 0x4445404C,
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.p0_mpwrdlctl = 0x38444542,
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.p1_mpwrdlctl = 0x4935493A,
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};
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/* MT41K256M16 (4Gb density) */
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static const struct mx6_ddr3_cfg mt41k256m16 = {
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.mem_speed = 1600,
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.density = 4,
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.width = 16,
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.banks = 8,
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.rowaddr = 15,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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#ifdef CONFIG_MX6_DDRCAL
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static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
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{
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struct mx6_mmdc_calibration calibration = {0};
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mmdc_read_calibration(sysinfo, &calibration);
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debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
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debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
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debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
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debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
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debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
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debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
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debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
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debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
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debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
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debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
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debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
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debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
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}
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static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
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{
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int ret;
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/* Perform DDR DRAM calibration */
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udelay(100);
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ret = mmdc_do_write_level_calibration(sysinfo);
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if (ret) {
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printf("DDR: Write level calibration error [%d]\n", ret);
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return;
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}
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ret = mmdc_do_dqs_calibration(sysinfo);
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if (ret) {
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printf("DDR: DQS calibration error [%d]\n", ret);
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return;
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}
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spl_dram_print_cal(sysinfo);
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}
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#endif /* CONFIG_MX6_DDRCAL */
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static void spl_dram_init(void)
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{
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struct mx6_ddr_sysinfo sysinfo = {
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/* width of data bus:0=16,1=32,2=64 */
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.dsize = 2,
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32, /* 32Gb per CS */
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/* single chip select */
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.ncs = 1,
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.cs1_mirror = 0,
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.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
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.rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
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.walat = 1, /* Write additional latency */
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.ralat = 5, /* Read additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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.bi_on = 1, /* Bank interleaving enabled */
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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.pd_fast_exit = 1, /* enable precharge power-down fast exit */
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.ddr_type = DDR_TYPE_DDR3,
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.refsel = 1, /* Refresh cycles at 32KHz */
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.refr = 7, /* 8 refresh commands per refresh cycle */
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};
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mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16);
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#ifdef CONFIG_MX6_DDRCAL
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spl_dram_perform_cal(&sysinfo);
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#endif
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}
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void board_boot_order(u32 *spl_boot_list)
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{
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u32 boot_device = spl_boot_device();
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u32 reg = imx6_src_get_boot_mode();
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reg = (reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT;
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debug("%s: boot device: 0x%x (0x4 SD, 0x6 eMMC)\n", __func__, reg);
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if (boot_device == BOOT_DEVICE_MMC1)
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if (reg == IMX6_BMODE_MMC || reg == IMX6_BMODE_EMMC)
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boot_device = BOOT_DEVICE_MMC2;
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spl_boot_list[0] = boot_device;
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/*
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* Below boot device is a 'fallback' - it shall always be possible to
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* boot from SD card
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*/
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spl_boot_list[1] = BOOT_DEVICE_MMC1;
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}
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void board_init_f(ulong dummy)
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{
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/* setup AIPS and disable watchdog */
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arch_cpu_init();
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ccgr_init();
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gpr_init();
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/* setup GP timer */
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timer_init();
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/* Early - pre reloc - driver model setup */
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spl_early_init();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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/* DDR initialization */
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spl_dram_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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}
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