mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
c5938c10ef
PBL flush command is restricted to CCSR memory space. So use WAIT PBI command to provide enough time for data to get flush in target memory. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> [York Sun: rewrap commit message] Reviewed-by: York Sun <york.sun@nxp.com>
28 lines
465 B
INI
28 lines
465 B
INI
#
|
|
# Copyright 2014 Freescale Semiconductor, Inc.
|
|
#
|
|
# SPDX-License-Identifier: GPL-2.0+
|
|
#
|
|
|
|
#PBI commands
|
|
#Initialize CPC1
|
|
09010000 00200400
|
|
09138000 00000000
|
|
091380c0 00000100
|
|
#512KB SRAM
|
|
09010100 00000000
|
|
09010104 fff80009
|
|
09010f00 08000000
|
|
#enable CPC1
|
|
09010000 80000000
|
|
#Configure LAW for CPC1
|
|
09000d00 00000000
|
|
09000d04 fff80000
|
|
09000d08 81000012
|
|
#Configure alternate space
|
|
09000010 00000000
|
|
09000014 ff000000
|
|
09000018 81000000
|
|
#Flush PBL data
|
|
091380c0 00100000
|