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https://github.com/brain-hackers/u-boot-brain
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06fc74102a
On i.MX7ULP B0, the DDR clock target is increased from 320Mhz to 380Mhz. We update DDR clock relevant settings to approach the target. But since the limitation on LCDIF pix clock for HDMI output (refer "mx7ulp_evk: Change APLL and its PFD0 frequencies"), we set DDR clock to 352.8Mhz (25.2Mhz * 14) by using the clock path: APLL PFD0 -> DDR CLK -> NIC0 -> NIC1 -> LCDIF clock To reduce the impact to entire system, the NIC0_DIV and NIC1_DIV are kept, so the divider 14 is calculated as: 14 = (NIC0_DIV + 1) * (NIC1_DIV + 1) * (LCDIF_PCC_DIV + 1) NIC0_DIV: 1 NIC1_DIV: 0 LCDIF_PCC_DIV: 6 APLL and APLL PFD0 settings: PFD0 FRAC: 27 APLL MULT: 22 APLL NUM: 1 APLL DENOM: 20 This patch applies the new settings for both DCD and plugin. There is no DDR script change on this new frequency. Overnight memtester is passed. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
217 lines
3.9 KiB
ArmAsm
217 lines
3.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2019 NXP
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*/
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#include <config.h>
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.macro imx7ulp_ddr_freq_decrease
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ldr r2, =0x403f0000
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ldr r3, =0x00000000
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str r3, [r2, #0xdc]
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ldr r2, =0x403e0000
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ldr r3, =0x01000020
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str r3, [r2, #0x40]
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ldr r3, =0x01000000
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str r3, [r2, #0x500]
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ldr r3, =0x80808080
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str r3, [r2, #0x50c]
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ldr r3, =0x00160002
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str r3, [r2, #0x508]
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ldr r3, =0x00000001
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str r3, [r2, #0x510]
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ldr r3, =0x00000014
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str r3, [r2, #0x514]
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ldr r3, =0x00000001
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str r3, [r2, #0x500]
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ldr r3, =0x01000000
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wait1:
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ldr r4, [r2, #0x500]
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and r4, r3
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cmp r4, r3
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bne wait1
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ldr r3, =0x8080801B
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str r3, [r2, #0x50c]
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ldr r3, =0x00000040
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wait2:
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ldr r4, [r2, #0x50c]
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and r4, r3
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cmp r4, r3
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bne wait2
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ldr r3, =0x00000001
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str r3, [r2, #0x30]
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ldr r3, =0x11000020
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str r3, [r2, #0x40]
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ldr r2, =0x403f0000
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ldr r3, =0x42000000
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str r3, [r2, #0xdc]
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.endm
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.macro imx7ulp_evk_ddr_setting
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imx7ulp_ddr_freq_decrease
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/* Enable MMDC PCC clock */
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ldr r2, =0x40b30000
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ldr r3, =0x40000000
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str r3, [r2, #0xac]
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/* Configure DDR pad */
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ldr r0, =0x40ad0000
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ldr r1, =0x00040000
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str r1, [r0, #0x128]
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ldr r1, =0x0
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str r1, [r0, #0xf8]
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ldr r1, =0x00000180
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str r1, [r0, #0xd8]
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ldr r1, =0x00000180
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str r1, [r0, #0x108]
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ldr r1, =0x00000180
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str r1, [r0, #0x104]
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ldr r1, =0x00010000
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str r1, [r0, #0x124]
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ldr r1, =0x0000018C
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str r1, [r0, #0x80]
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ldr r1, =0x0000018C
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str r1, [r0, #0x84]
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ldr r1, =0x0000018C
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str r1, [r0, #0x88]
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ldr r1, =0x0000018C
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str r1, [r0, #0x8c]
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ldr r1, =0x00010000
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str r1, [r0, #0x120]
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ldr r1, =0x00000180
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str r1, [r0, #0x10c]
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ldr r1, =0x00000180
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str r1, [r0, #0x110]
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ldr r1, =0x00000180
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str r1, [r0, #0x114]
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ldr r1, =0x00000180
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str r1, [r0, #0x118]
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ldr r1, =0x00000180
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str r1, [r0, #0x90]
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ldr r1, =0x00000180
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str r1, [r0, #0x94]
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ldr r1, =0x00000180
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str r1, [r0, #0x98]
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ldr r1, =0x00000180
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str r1, [r0, #0x9c]
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ldr r1, =0x00040000
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str r1, [r0, #0xe0]
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ldr r1, =0x00040000
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str r1, [r0, #0xe4]
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ldr r0, =0x40ab0000
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ldr r1, =0x00008000
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str r1, [r0, #0x1c]
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ldr r1, =0xA1390003
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str r1, [r0, #0x800]
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ldr r1, =0x0D3900A0
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str r1, [r0, #0x85c]
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ldr r1, =0x00400000
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str r1, [r0, #0x890]
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ldr r1, =0x40404040
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str r1, [r0, #0x848]
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ldr r1, =0x40404040
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str r1, [r0, #0x850]
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ldr r1, =0x33333333
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str r1, [r0, #0x81c]
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ldr r1, =0x33333333
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str r1, [r0, #0x820]
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ldr r1, =0x33333333
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str r1, [r0, #0x824]
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ldr r1, =0x33333333
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str r1, [r0, #0x828]
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ldr r1, =0x24922492
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str r1, [r0, #0x8c0]
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ldr r1, =0x00000800
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str r1, [r0, #0x8b8]
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ldr r1, =0x00020052
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str r1, [r0, #0x4]
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ldr r1, =0x292C42F3
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str r1, [r0, #0xc]
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ldr r1, =0x00100A22
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str r1, [r0, #0x10]
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ldr r1, =0x00120556
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str r1, [r0, #0x38]
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ldr r1, =0x00C700DB
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str r1, [r0, #0x14]
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ldr r1, =0x00211718
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str r1, [r0, #0x18]
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ldr r1, =0x0F9F26D2
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str r1, [r0, #0x2c]
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ldr r1, =0x009F0E10
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str r1, [r0, #0x30]
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ldr r1, =0x0000003F
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str r1, [r0, #0x40]
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ldr r1, =0xC3190000
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str r1, [r0, #0x0]
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ldr r1, =0x00008010
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str r1, [r0, #0x1c]
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ldr r1, =0x00008018
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str r1, [r0, #0x1c]
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ldr r1, =0x003F8030
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str r1, [r0, #0x1c]
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ldr r1, =0x003F8038
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str r1, [r0, #0x1c]
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ldr r1, =0xFF0A8030
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str r1, [r0, #0x1c]
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ldr r1, =0xFF0A8038
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str r1, [r0, #0x1c]
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ldr r1, =0x04028030
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str r1, [r0, #0x1c]
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ldr r1, =0x04028038
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str r1, [r0, #0x1c]
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ldr r1, =0x83018030
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str r1, [r0, #0x1c]
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ldr r1, =0x83018038
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str r1, [r0, #0x1c]
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ldr r1, =0x01038030
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str r1, [r0, #0x1c]
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ldr r1, =0x01038038
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str r1, [r0, #0x1c]
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ldr r1, =0x20000000
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str r1, [r0, #0x83c]
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ldr r1, =0x00001800
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str r1, [r0, #0x20]
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ldr r1, =0xA1310000
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str r1, [r0, #0x800]
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ldr r1, =0x00020052
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str r1, [r0, #0x4]
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ldr r1, =0x00011006
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str r1, [r0, #0x404]
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ldr r1, =0x00000000
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str r1, [r0, #0x1c]
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.endm
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.macro imx7ulp_clock_gating
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.endm
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.macro imx7ulp_qos_setting
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.endm
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.macro imx7ulp_ddr_setting
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imx7ulp_evk_ddr_setting
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.endm
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/* include the common plugin code here */
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#include <asm/arch/mx7ulp_plugin.S>
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