mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
d714a75fd4
CONFIG_SECURE_BOOT is too generic and forbids to use it for cross architecture purposes. If Secure Boot is required for imx, this means to enable and use the HAB processor in the soc. Signed-off-by: Stefano Babic <sbabic@denx.de>
139 lines
2.9 KiB
INI
139 lines
2.9 KiB
INI
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi/sd/nand/onenand, qspi/nor
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*/
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BOOT_FROM sd
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/*
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* Secure boot support
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*/
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#ifdef CONFIG_IMX_HAB
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CSF CONFIG_CSF_SIZE
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#endif
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/* Enable all clocks */
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DATA 4 0x020c4068 0xffffffff
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DATA 4 0x020c406c 0xffffffff
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DATA 4 0x020c4070 0xffffffff
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DATA 4 0x020c4074 0xffffffff
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DATA 4 0x020c4078 0xffffffff
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DATA 4 0x020c407c 0xffffffff
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DATA 4 0x020c4080 0xffffffff
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DATA 4 0x020c4084 0xffffffff
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/* IOMUX - DDR IO Type */
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DATA 4 0x020e0618 0x000c0000
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DATA 4 0x020e05fc 0x00000000
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/* Clock */
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DATA 4 0x020e032c 0x00000030
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/* Address */
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DATA 4 0x020e0300 0x00000020
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DATA 4 0x020e02fc 0x00000020
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DATA 4 0x020e05f4 0x00000020
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/* Control */
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DATA 4 0x020e0340 0x00000020
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DATA 4 0x020e0320 0x00000000
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DATA 4 0x020e0310 0x00000020
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DATA 4 0x020e0314 0x00000020
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DATA 4 0x020e0614 0x00000020
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/* Data Strobe */
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DATA 4 0x020e05f8 0x00020000
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DATA 4 0x020e0330 0x00000028
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DATA 4 0x020e0334 0x00000028
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DATA 4 0x020e0338 0x00000028
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DATA 4 0x020e033c 0x00000028
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/* Data */
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DATA 4 0x020e0608 0x00020000
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DATA 4 0x020e060c 0x00000028
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DATA 4 0x020e0610 0x00000028
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DATA 4 0x020e061c 0x00000028
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DATA 4 0x020e0620 0x00000028
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DATA 4 0x020e02ec 0x00000028
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DATA 4 0x020e02f0 0x00000028
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DATA 4 0x020e02f4 0x00000028
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DATA 4 0x020e02f8 0x00000028
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/* Calibrations - ZQ */
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DATA 4 0x021b0800 0xa1390003
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/* Write leveling */
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DATA 4 0x021b080c 0x00290025
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DATA 4 0x021b0810 0x00220022
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/* DQS Read Gate */
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DATA 4 0x021b083c 0x41480144
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DATA 4 0x021b0840 0x01340130
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/* Read/Write Delay */
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DATA 4 0x021b0848 0x3C3E4244
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DATA 4 0x021b0850 0x34363638
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/* Read data bit delay */
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DATA 4 0x021b081c 0x33333333
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DATA 4 0x021b0820 0x33333333
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DATA 4 0x021b0824 0x33333333
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DATA 4 0x021b0828 0x33333333
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/* Complete calibration by forced measurement */
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DATA 4 0x021b08b8 0x00000800
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/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
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DATA 4 0x021b0004 0x0002002d
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DATA 4 0x021b0008 0x00333030
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DATA 4 0x021b000c 0x676b52f3
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DATA 4 0x021b0010 0xb66d8b63
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DATA 4 0x021b0014 0x01ff00db
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DATA 4 0x021b0018 0x00011740
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DATA 4 0x021b001c 0x00008000
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DATA 4 0x021b002c 0x000026d2
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DATA 4 0x021b0030 0x006b1023
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DATA 4 0x021b0040 0x0000005f
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DATA 4 0x021b0000 0x84190000
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/* Initialize MT41K256M16HA-125 - MR2 */
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DATA 4 0x021b001c 0x04008032
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/* MR3 */
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DATA 4 0x021b001c 0x00008033
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/* MR1 */
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DATA 4 0x021b001c 0x00048031
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/* MR0 */
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DATA 4 0x021b001c 0x05208030
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/* DDR device ZQ calibration */
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DATA 4 0x021b001c 0x04008040
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/* Final DDR setup, before operation start */
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DATA 4 0x021b0020 0x00000800
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DATA 4 0x021b0818 0x00011117
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DATA 4 0x021b001c 0x00000000
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