mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
50 lines
1.7 KiB
C
50 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2016 Freescale Semiconductor
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*/
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#ifndef __CPLD_H__
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#define __CPLD_H__
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/*
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* CPLD register set of LS1046ARDB board-specific.
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* CPLD Revision: V2.1
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*/
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struct cpld_data {
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u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
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u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
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u8 pcba_ver; /* 0x2 - PCBA Revision Register */
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u8 system_rst; /* 0x3 - system reset register */
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u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */
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u8 cfg_rcw_src1; /* 0x5 - RCW Source Location POR Regsiter 1 */
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u8 cfg_rcw_src2; /* 0x6 - RCW Source Location POR Regsiter 2 */
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u8 vbank; /* 0x7 - QSPI Flash Bank Setting Register */
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u8 sysclk_sel; /* 0x8 - System clock POR Register */
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u8 uart_sel; /* 0x9 - UART1 Connection Control Register */
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u8 sd1refclk_sel; /* 0xA - */
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u8 rgmii_1588_sel; /* 0xB - */
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u8 reg_1588_clk_sel; /* 0xC - */
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u8 status_led; /* 0xD - */
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u8 global_rst; /* 0xE - */
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u8 sd_emmc; /* 0xF - SD/EMMC Interface Control Regsiter */
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u8 vdd_en; /* 0x10 - VDD Voltage Control Enable Register */
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u8 vdd_sel; /* 0x11 - VDD Voltage Control Register */
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};
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u8 cpld_read(unsigned int reg);
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void cpld_write(unsigned int reg, u8 value);
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void cpld_rev_bit(unsigned char *value);
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void cpld_select_core_volt(bool en_0v9);
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#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
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#define CPLD_WRITE(reg, value) \
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cpld_write(offsetof(struct cpld_data, reg), value)
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/* CPLD on IFC */
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#define CPLD_SW_MUX_BANK_SEL 0x40
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#define CPLD_BANK_SEL_MASK 0x07
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#define CPLD_BANK_SEL_ALTBANK 0x04
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#define CPLD_CFG_RCW_SRC_QSPI 0x044
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#define CPLD_CFG_RCW_SRC_SD 0x040
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#endif
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