mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
401d1c4f5d
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
121 lines
2.6 KiB
C
121 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright 2019 NXP
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <env.h>
|
|
#include <errno.h>
|
|
#include <init.h>
|
|
#include <miiphy.h>
|
|
#include <netdev.h>
|
|
#include <linux/delay.h>
|
|
#include <asm/global_data.h>
|
|
#include <asm/mach-imx/iomux-v3.h>
|
|
#include <asm-generic/gpio.h>
|
|
#include <asm/arch/imx8mp_pins.h>
|
|
#include <asm/arch/clock.h>
|
|
#include <asm/arch/sys_proto.h>
|
|
#include <asm/mach-imx/gpio.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
|
|
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
|
|
|
|
static iomux_v3_cfg_t const uart_pads[] = {
|
|
MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
};
|
|
|
|
static iomux_v3_cfg_t const wdog_pads[] = {
|
|
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
|
|
};
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
|
|
|
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
|
|
|
set_wdog_reset(wdog);
|
|
|
|
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void setup_fec(void)
|
|
{
|
|
struct iomuxc_gpr_base_regs *gpr =
|
|
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
|
|
|
/* Enable RGMII TX clk output */
|
|
setbits_le32(&gpr->gpr[1], BIT(22));
|
|
}
|
|
|
|
#define EQOS_RST_PAD IMX_GPIO_NR(4, 22)
|
|
static iomux_v3_cfg_t const eqos_rst_pads[] = {
|
|
MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
};
|
|
|
|
static void setup_iomux_eqos(void)
|
|
{
|
|
imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
|
|
ARRAY_SIZE(eqos_rst_pads));
|
|
|
|
gpio_request(EQOS_RST_PAD, "eqos_rst");
|
|
gpio_direction_output(EQOS_RST_PAD, 0);
|
|
mdelay(15);
|
|
gpio_direction_output(EQOS_RST_PAD, 1);
|
|
mdelay(100);
|
|
}
|
|
|
|
static int setup_eqos(void)
|
|
{
|
|
struct iomuxc_gpr_base_regs *gpr =
|
|
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
|
|
|
setup_iomux_eqos();
|
|
|
|
/* set INTF as RGMII, enable RGMII TXC clock */
|
|
clrsetbits_le32(&gpr->gpr[1],
|
|
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
|
|
setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
|
|
|
|
return set_clk_eqos(ENET_125MHZ);
|
|
}
|
|
|
|
#if CONFIG_IS_ENABLED(NET)
|
|
int board_phy_config(struct phy_device *phydev)
|
|
{
|
|
if (phydev->drv->config)
|
|
phydev->drv->config(phydev);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int board_init(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
if (CONFIG_IS_ENABLED(FEC_MXC)) {
|
|
setup_fec();
|
|
|
|
if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
|
|
ret = setup_eqos();
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int board_late_init(void)
|
|
{
|
|
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
|
env_set("board_name", "EVK");
|
|
env_set("board_rev", "iMX8MP");
|
|
#endif
|
|
|
|
return 0;
|
|
}
|