mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
107 lines
3.7 KiB
C
107 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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* Author: Shaveta Leekha <shaveta@freescale.com>
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*/
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#ifndef __IDT8T49N222A_SERDES_CLK_H_
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#define __IDT8T49N222A_SERDES_CLK_H_ 1
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#include <common.h>
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#include <i2c.h>
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#include "qixis.h"
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#include "../b4860qds/b4860qds_qixis.h"
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#include <errno.h>
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#define NUM_IDT_REGS 23
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#define NUM_IDT_REGS_FEEDBACK 12
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#define NUM_IDT_REGS_156_25 11
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/* CLK */
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enum serdes_refclk {
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SERDES_REFCLK_100, /* refclk 100Mhz */
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SERDES_REFCLK_122_88, /* refclk 122.88Mhz */
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SERDES_REFCLK_125, /* refclk 125Mhz */
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SERDES_REFCLK_156_25, /* refclk 156.25Mhz */
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SERDES_REFCLK_NONE = -1,
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};
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/* configuration values for IDT registers for Output Refclks:
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* Refclk1 = 122.88MHz Refclk2 = 122.88MHz
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*/
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static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00},
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{0x02, 0x9F}, {0x03, 0x00}, {0x04, 0x0B}, {0x05, 0x00},
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{0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
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{0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
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{0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x12}, {0x11, 0x12},
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{0x12, 0xB9}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
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{0x16, 0xA0} };
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/* configuration values for IDT registers for Output Refclks:
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* Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz
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*/
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static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00},
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{0x02, 0x00}, {0x03, 0x00}, {0x04, 0x0A}, {0x05, 0x00},
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{0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
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{0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
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{0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x14}, {0x11, 0x14},
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{0x12, 0x35}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
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{0x16, 0xA0} };
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/* Reconfiguration values for some of IDT registers for
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* Output Refclks:
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* Refclk1 = 122.88MHz Refclk2 = 122.88MHz
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* and with feedback as 1
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*/
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static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7},
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{0x04, 0x89}, {0x06, 0xC3}, {0x08, 0xC0}, {0x0A, 0x07},
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{0x0C, 0x80}, {0x10, 0x10}, {0x11, 0x10}, {0x12, 0x1B},
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{0x14, 0x00}, {0x15, 0xE8} };
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/* configuration values for IDT registers for Output Refclks:
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* Refclk1 : 156.25MHz Refclk2 : 156.25MHz
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*/
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static const u8 idt_conf_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
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{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
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{0x10, 0x10}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
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{0x15, 0xE8} };
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/* configuration values for IDT registers for Output Refclks:
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* Refclk1 : 100MHz Refclk2 : 156.25MHz
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*/
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static const u8 idt_conf_100_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
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{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
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{0x10, 0x19}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
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{0x15, 0xE8} };
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/* configuration values for IDT registers for Output Refclks:
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* Refclk1 : 125MHz Refclk2 : 156.25MHz
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*/
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static const u8 idt_conf_125_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
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{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
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{0x10, 0x14}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
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{0x15, 0xE8} };
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/* configuration values for IDT registers for Output Refclks:
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* Refclk1 : 156.25MHz Refclk2 : 100MHz
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*/
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static const u8 idt_conf_156_25_100[11][2] = { {0x04, 0x19}, {0x06, 0x03},
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{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
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{0x10, 0x10}, {0x11, 0x19}, {0x12, 0xB5}, {0x13, 0x3C},
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{0x15, 0xE8} };
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/* configuration values for IDT registers for Output Refclks:
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* Refclk1 : 156.25MHz Refclk2 : 125MHz
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*/
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static const u8 idt_conf_156_25_125[11][2] = { {0x04, 0x19}, {0x06, 0x03},
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{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
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{0x10, 0x10}, {0x11, 0x14}, {0x12, 0xB5}, {0x13, 0x3C},
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{0x15, 0xE8} };
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int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
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enum serdes_refclk refclk1,
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enum serdes_refclk refclk2, u8 feedback);
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#endif /*__IDT8T49N222A_SERDES_CLK_H_ */
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