mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
401d1c4f5d
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
258 lines
6.6 KiB
C
258 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <init.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/atmel_pio4.h>
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#include <asm/arch/atmel_mpddrc.h>
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#include <asm/arch/atmel_sdhci.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/sama5d2.h>
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extern void at91_pda_detect(void);
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_DM_VIDEO
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at91_video_show_board_info();
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#endif
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at91_pda_detect();
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return 0;
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}
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#endif
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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static void board_uart0_hw_init(void)
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{
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atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */
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atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
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at91_periph_clk_enable(ATMEL_ID_UART0);
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}
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void board_debug_uart_init(void)
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{
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board_uart0_hw_init();
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}
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#endif
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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#ifdef CONFIG_DEBUG_UART
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debug_uart_init();
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#endif
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return 0;
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}
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#endif
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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#ifdef CONFIG_SPI_FLASH_SFDP_SUPPORT
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at91_spi_nor_set_ethaddr();
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#endif
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return 0;
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}
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#endif
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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/* SPL */
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#ifdef CONFIG_SPL_BUILD
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static void board_leds_init(void)
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{
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atmel_pio4_set_pio_output(AT91_PIO_PORTA, 6, 0); /* RED */
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atmel_pio4_set_pio_output(AT91_PIO_PORTA, 7, 1); /* GREEN */
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atmel_pio4_set_pio_output(AT91_PIO_PORTA, 8, 0); /* BLUE */
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}
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#ifdef CONFIG_SD_BOOT
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void spl_mmc_init(void)
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{
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* CMD */
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* DAT0 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* DAT1 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* DAT2 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* DAT3 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* CK */
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atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CD */
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at91_periph_clk_enable(ATMEL_ID_SDMMC0);
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}
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#endif
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#ifdef CONFIG_QSPI_BOOT
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void spl_qspi_init(void)
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{
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atmel_pio4_set_d_periph(AT91_PIO_PORTB, 5, 0); /* SCK */
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atmel_pio4_set_d_periph(AT91_PIO_PORTB, 6, 0); /* CS */
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atmel_pio4_set_d_periph(AT91_PIO_PORTB, 7, 0); /* IO0 */
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atmel_pio4_set_d_periph(AT91_PIO_PORTB, 8, 0); /* IO1 */
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atmel_pio4_set_d_periph(AT91_PIO_PORTB, 9, 0); /* IO2 */
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atmel_pio4_set_d_periph(AT91_PIO_PORTB, 10, 0); /* IO3 */
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at91_periph_clk_enable(ATMEL_ID_QSPI1);
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}
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#endif
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void spl_board_init(void)
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{
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board_leds_init();
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#ifdef CONFIG_SD_BOOT
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spl_mmc_init();
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#endif
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#ifdef CONFIG_QSPI_BOOT
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spl_qspi_init();
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#endif
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}
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void spl_display_print(void)
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{
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}
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static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
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{
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ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR2_SDRAM);
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ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_9 |
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ATMEL_MPDDRC_CR_NR_ROW_14 |
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ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
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ATMEL_MPDDRC_CR_ZQ_SHORT |
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ATMEL_MPDDRC_CR_NB_8BANKS |
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ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
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ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
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ddrc->lpddr23_lpr = ATMEL_MPDDRC_LPDDR23_LPR_DS(0x3);
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/*
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* The AD220032D average time between REFRESH commands (Trefi): 3.9us
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* 3.9us * 164MHz = 639.6 = 0x27F.
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*/
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ddrc->rtr = 0x27f;
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/* Enable Adjust Refresh Rate */
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ddrc->rtr |= ATMEL_MPDDRC_RTR_ADJ_REF;
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ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
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(3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
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(4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
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(11 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
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(4 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
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(2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
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(2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
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(5 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
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ddrc->tpr1 = ((21 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
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(0 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
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(23 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
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(2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
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ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
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(0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
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(4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
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(2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
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(10 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
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ddrc->tim_cal = ATMEL_MPDDRC_CALR_ZQCS(15);
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/*
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* According to the sama5d2 datasheet and the following values:
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* T Sens = 0.75%/C, V Sens = 0.2%/mV, T driftrate = 1C/sec and V driftrate = 15 mV/s
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* Warning: note that the values T driftrate and V driftrate are dependent on
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* the application environment.
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* ZQCS period is 1.5 / ((0.75 x 1) + (0.2 x 15)) = 0.4s
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* If Trefi is 3.9us, we have: 400000 / 3.9 = 102564: we can maximize
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* this timer to 0xFFFE.
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*/
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ddrc->cal_mr4 = ATMEL_MPDDRC_CAL_MR4_COUNT_CAL(0xFFFE);
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/*
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* MR4 Read interval is dependent on the application environment.
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* Here, we want to maximize this value as temperature is supposed
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* to vary slowly in the application chosen.
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* If Trefi is 3.9us, we have:
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* (0xFFFE) 65534 x 3.9 = 0.25s between MR4 reads.
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*/
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ddrc->cal_mr4 |= ATMEL_MPDDRC_CAL_MR4_MR4R(0xFFFE);
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}
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void mem_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
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struct atmel_mpddrc_config ddrc_config;
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u32 reg;
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at91_periph_clk_enable(ATMEL_ID_MPDDRC);
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writel(AT91_PMC_DDR, &pmc->scer);
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ddrc_conf(&ddrc_config);
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reg = readl(&mpddrc->io_calibr);
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reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
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reg |= ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_48;
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reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
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reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
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writel(reg, &mpddrc->io_calibr);
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writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
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&mpddrc->rd_data_path);
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lpddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
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}
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void at91_pmc_init(void)
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{
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u32 tmp;
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/*
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* while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
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* so we need to slow down and configure MCKR accordingly.
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* This is why we have a special flavor of the switching function.
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*/
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tmp = AT91_PMC_MCKR_PLLADIV_2 |
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AT91_PMC_MCKR_MDIV_3 |
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AT91_PMC_MCKR_CSS_MAIN;
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at91_mck_init_down(tmp);
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tmp = AT91_PMC_PLLAR_29 |
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AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
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AT91_PMC_PLLXR_MUL(40) |
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AT91_PMC_PLLXR_DIV(1);
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at91_plla_init(tmp);
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tmp = AT91_PMC_MCKR_H32MXDIV |
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AT91_PMC_MCKR_PLLADIV_2 |
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AT91_PMC_MCKR_MDIV_3 |
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AT91_PMC_MCKR_CSS_PLLA;
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at91_mck_init(tmp);
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}
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#endif
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