mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
75 lines
2.2 KiB
C
75 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2011
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* Linaro
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* Linus Walleij <linus.walleij@linaro.org>
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* Register definitions for the System Controller (SC) and
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* the similar "CP Controller" found in the ARM Integrator/AP and
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* Integrator/CP reference designs
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*/
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#ifndef __ARM_SC_H
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#define __ARM_SC_H
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#define SC_BASE 0x11000000
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/*
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* The system controller registers
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*/
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#define SC_ID_OFFSET 0x00
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#define SC_OSC_OFFSET 0x04
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/* Setting this bit switches to 25 MHz mode, clear means 33 MHz */
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#define SC_OSC_DIVXY (1 << 8)
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#define SC_CTRLS_OFFSET 0x08
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#define SC_CTRLC_OFFSET 0x0C
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/* Set bits by writing CTRLS, clear bits by writing CTRLC */
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#define SC_CTRL_SOFTRESET (1 << 0)
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#define SC_CTRL_FLASHVPP (1 << 1)
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#define SC_CTRL_FLASHWP (1 << 2)
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#define SC_CTRL_UART1DTR (1 << 4)
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#define SC_CTRL_UART1RTS (1 << 5)
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#define SC_CTRL_UART0DTR (1 << 6)
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#define SC_CTRL_UART0RTS (1 << 7)
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#define SC_DEC_OFFSET 0x10
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#define SC_ARB_OFFSET 0x14
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#define SC_PCI_OFFSET 0x18
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#define SC_PCI_PCIEN (1 << 0)
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#define SC_PCI_PCIBINT_CLR (1 << 1)
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#define SC_LOCK_OFFSET 0x1C
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#define SC_LBFADDR_OFFSET 0x20
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#define SC_LBFCODE_OFFSET 0x24
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#define SC_ID (SC_BASE + SC_ID_OFFSET)
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#define SC_OSC (SC_BASE + SC_OSC_OFFSET)
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#define SC_CTRLS (SC_BASE + SC_CTRLS_OFFSET)
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#define SC_CTRLC (SC_BASE + SC_CTRLC_OFFSET)
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#define SC_DEC (SC_BASE + SC_DEC_OFFSET)
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#define SC_ARB (SC_BASE + SC_ARB_OFFSET)
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#define SC_PCI (SC_BASE + SC_PCI_OFFSET)
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#define SC_LOCK (SC_BASE + SC_LOCK_OFFSET)
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#define SC_LBFADDR (SC_BASE + SC_LBFADDR_OFFSET)
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#define SC_LBFCODE (SC_BASE + SC_LBFCODE_OFFSET)
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/*
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* The Integrator/CP as a smaller set of registers, at a different
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* offset - probably not to disturb old software.
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*/
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#define CP_BASE 0xCB000000
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#define CP_IDFIELD_OFFSET 0x00
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#define CP_FLASHPROG_OFFSET 0x04
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#define CP_FLASHPROG_FLVPPEN (1 << 0)
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#define CP_FLASHPROG_FLWREN (1 << 1)
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#define CP_FLASHPROG_FLASHSIZE (1 << 2)
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#define CP_FLASHPROG_EXTRABANK (1 << 3)
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#define CP_INTREG_OFFSET 0x08
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#define CP_DECODE_OFFSET 0x0C
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#define CP_IDFIELD (CP_BASE + CP_ID_OFFSET)
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#define CP_FLASHPROG (CP_BASE + CP_FLASHPROG_OFFSET)
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#define CP_INTREG (CP_BASE + CP_INTREG_OFFSET)
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#define CP_DECODE (CP_BASE + CP_DECODE_OFFSET)
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#endif
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