448 lines
12 KiB
C
448 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*
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* https://spdx.org/licenses
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*/
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#ifndef __BOARD_DDR_H__
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#define __BOARD_DDR_H__
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#define OCTEON_EBB7304_DRAM_SOCKET_CONFIGURATION0 \
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{ {0x1050, 0x0}, {NULL, NULL} }, { {0x1051, 0x0}, {NULL, NULL} }
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#define OCTEON_EBB7304_DRAM_SOCKET_CONFIGURATION1 \
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{ {0x1052, 0x0}, {NULL, NULL} }, { {0x1053, 0x0}, {NULL, NULL} }
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#define OCTEON_EBB7304_BOARD_EEPROM_TWSI_ADDR 0x56
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/*
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* Local copy of these parameters to allow for customization for this
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* board design. The generic version resides in lib_octeon_shared.h.
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*/
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/* LMC0_MODEREG_PARAMS1 */
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#define OCTEON_EBB7304_MODEREG_PARAMS1_1RANK_1SLOT \
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{ \
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.cn78xx = { \
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.pasr_00 = 0, \
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.asr_00 = 0, \
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.srt_00 = 0, \
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.rtt_wr_00 = ddr4_rttwr_80ohm & 3, \
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.rtt_wr_00_ext = (ddr4_rttwr_80ohm >> 2) & 1, \
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.dic_00 = ddr4_dic_34ohm, \
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.rtt_nom_00 = 0, \
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.pasr_01 = 0, \
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.asr_01 = 0, \
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.srt_01 = 0, \
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.rtt_wr_01 = 0, \
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.dic_01 = ddr4_dic_34ohm, \
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.rtt_nom_01 = 0, \
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.pasr_10 = 0, \
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.asr_10 = 0, \
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.srt_10 = 0, \
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.rtt_wr_10 = 0, \
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.dic_10 = ddr4_dic_34ohm, \
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.rtt_nom_10 = 0, \
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.pasr_11 = 0, \
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.asr_11 = 0, \
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.srt_11 = 0, \
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.rtt_wr_11 = 0, \
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.dic_11 = ddr4_dic_34ohm, \
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.rtt_nom_11 = 0, \
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} \
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}
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#define OCTEON_EBB7304_MODEREG_PARAMS1_1RANK_2SLOT \
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{ \
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.cn78xx = { \
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.pasr_00 = 0, \
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.asr_00 = 0, \
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.srt_00 = 0, \
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.rtt_wr_00 = ddr4_rttwr_80ohm & 3, \
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.rtt_wr_00_ext = (ddr4_rttwr_80ohm >> 2) & 1, \
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.dic_00 = ddr4_dic_34ohm, \
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.rtt_nom_00 = 0, \
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.pasr_01 = 0, \
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.asr_01 = 0, \
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.srt_01 = 0, \
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.rtt_wr_01 = 0, \
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.dic_01 = ddr4_dic_34ohm, \
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.rtt_nom_01 = 0, \
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.pasr_10 = 0, \
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.asr_10 = 0, \
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.srt_10 = 0, \
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.rtt_wr_10 = ddr4_rttwr_80ohm & 3, \
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.rtt_wr_10_ext = (ddr4_rttwr_80ohm >> 2) & 1, \
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.dic_10 = ddr4_dic_34ohm, \
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.rtt_nom_10 = 0, \
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.pasr_11 = 0, \
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.asr_11 = 0, \
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.srt_11 = 0, \
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.rtt_wr_11 = 0, \
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.dic_11 = ddr4_dic_34ohm, \
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.rtt_nom_11 = 0 \
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} \
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}
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#define OCTEON_EBB7304_MODEREG_PARAMS1_2RANK_1SLOT \
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{ \
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.cn78xx = { \
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.pasr_00 = 0, \
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.asr_00 = 0, \
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.srt_00 = 0, \
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.rtt_wr_00 = ddr4_rttwr_240ohm, \
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.dic_00 = ddr4_dic_34ohm, \
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.rtt_nom_00 = 0, \
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.pasr_01 = 0, \
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.asr_01 = 0, \
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.srt_01 = 0, \
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.rtt_wr_01 = ddr4_rttwr_240ohm, \
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.dic_01 = ddr4_dic_34ohm, \
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.rtt_nom_01 = 0, \
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.pasr_10 = 0, \
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.asr_10 = 0, \
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.srt_10 = 0, \
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.dic_10 = ddr4_dic_34ohm, \
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.rtt_nom_10 = 0, \
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.pasr_11 = 0, \
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.asr_11 = 0, \
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.srt_11 = 0, \
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.rtt_wr_11 = 0, \
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.dic_11 = ddr4_dic_34ohm, \
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.rtt_nom_11 = 0, \
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} \
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}
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#define OCTEON_EBB7304_MODEREG_PARAMS1_2RANK_2SLOT \
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{ \
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.cn78xx = { \
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.pasr_00 = 0, \
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.asr_00 = 0, \
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.srt_00 = 0, \
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.rtt_wr_00 = ddr4_rttwr_240ohm, \
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.dic_00 = ddr4_dic_34ohm, \
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.rtt_nom_00 = ddr4_rttnom_120ohm, \
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.pasr_01 = 0, \
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.asr_01 = 0, \
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.srt_01 = 0, \
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.rtt_wr_01 = ddr4_rttwr_240ohm, \
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.dic_01 = ddr4_dic_34ohm, \
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.rtt_nom_01 = ddr4_rttnom_120ohm, \
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.pasr_10 = 0, \
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.asr_10 = 0, \
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.srt_10 = 0, \
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.rtt_wr_10 = ddr4_rttwr_240ohm, \
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.dic_10 = ddr4_dic_34ohm, \
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.rtt_nom_10 = ddr4_rttnom_120ohm, \
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.pasr_11 = 0, \
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.asr_11 = 0, \
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.srt_11 = 0, \
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.rtt_wr_11 = ddr4_rttwr_240ohm, \
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.dic_11 = ddr4_dic_34ohm, \
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.rtt_nom_11 = ddr4_rttnom_120ohm, \
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} \
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}
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#define OCTEON_EBB7304_MODEREG_PARAMS1_4RANK_1SLOT \
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{ \
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.cn78xx = { \
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.pasr_00 = 0, \
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.asr_00 = 0, \
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.srt_00 = 0, \
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.rtt_wr_00 = rttwr_60ohm, \
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.dic_00 = dic_34ohm, \
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.rtt_nom_00 = rttnom_20ohm, \
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.pasr_01 = 0, \
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.asr_01 = 0, \
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.srt_01 = 0, \
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.rtt_wr_01 = rttwr_60ohm, \
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.dic_01 = dic_34ohm, \
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.rtt_nom_01 = rttnom_none, \
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.pasr_10 = 0, \
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.asr_10 = 0, \
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.srt_10 = 0, \
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.rtt_wr_10 = rttwr_60ohm, \
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.dic_10 = dic_34ohm, \
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.rtt_nom_10 = rttnom_20ohm, \
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.pasr_11 = 0, \
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.asr_11 = 0, \
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.srt_11 = 0, \
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.rtt_wr_11 = rttwr_60ohm, \
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.dic_11 = dic_34ohm, \
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.rtt_nom_11 = rttnom_none, \
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} \
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}
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#define OCTEON_EBB7304_MODEREG_PARAMS2_1RANK_1SLOT \
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{ \
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.cn78xx = { \
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.rtt_park_00 = ddr4_rttpark_60ohm, \
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.vref_value_00 = 0x22, \
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.vref_range_00 = 0, \
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.rtt_park_01 = 0, \
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.vref_value_01 = 0, \
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.vref_range_01 = 0, \
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.rtt_park_10 = 0, \
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.vref_value_10 = 0, \
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.vref_range_10 = 0, \
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.rtt_park_11 = 0, \
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.vref_value_11 = 0, \
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.vref_range_11 = 0 \
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} \
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}
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/* FIX */
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#define OCTEON_EBB7304_MODEREG_PARAMS2_1RANK_2SLOT \
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{ \
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.cn78xx = { \
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.rtt_park_00 = ddr4_rttpark_48ohm, \
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.vref_value_00 = 0x1f, \
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.vref_range_00 = 0, \
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.rtt_park_01 = 0, \
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.vref_value_01 = 0, \
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.vref_range_01 = 0, \
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.rtt_park_10 = ddr4_rttpark_48ohm, \
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.vref_value_10 = 0x1f, \
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.vref_range_10 = 0, \
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.rtt_park_11 = 0, \
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.vref_value_11 = 0, \
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.vref_range_11 = 0 \
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} \
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}
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#define OCTEON_EBB7304_MODEREG_PARAMS2_2RANK_1SLOT \
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{ \
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.cn78xx = { \
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.rtt_park_00 = ddr4_rttpark_120ohm, \
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.vref_value_00 = 0x19, \
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.vref_range_00 = 0, \
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.rtt_park_01 = ddr4_rttpark_120ohm, \
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.vref_value_01 = 0x19, \
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.vref_range_01 = 0, \
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.rtt_park_10 = 0, \
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.vref_value_10 = 0, \
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.vref_range_10 = 0, \
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.rtt_park_11 = 0, \
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.vref_value_11 = 0, \
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.vref_range_11 = 0 \
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} \
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}
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#define OCTEON_EBB7304_MODEREG_PARAMS2_2RANK_2SLOT \
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{ \
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.cn78xx = { \
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.rtt_park_00 = ddr4_rttpark_60ohm, \
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.vref_value_00 = 0x19, \
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.vref_range_00 = 0, \
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.rtt_park_01 = ddr4_rttpark_60ohm, \
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.vref_value_01 = 0x19, \
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.vref_range_01 = 0, \
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.rtt_park_10 = ddr4_rttpark_60ohm, \
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.vref_value_10 = 0x19, \
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.vref_range_10 = 0, \
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.rtt_park_11 = ddr4_rttpark_60ohm, \
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.vref_value_11 = 0x19, \
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.vref_range_11 = 0 \
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} \
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}
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#define OCTEON_EBB7304_MODEREG_PARAMS2_4RANK_1SLOT \
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{ \
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.cn78xx = { \
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.rtt_park_00 = ddr4_rttpark_80ohm, \
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.vref_value_00 = 0x1f, \
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.vref_range_00 = 0, \
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.rtt_park_01 = ddr4_rttpark_80ohm, \
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.vref_value_01 = 0x1f, \
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.vref_range_01 = 0, \
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.rtt_park_10 = 0, \
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.vref_value_10 = 0, \
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.vref_range_10 = 0, \
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.rtt_park_11 = 0, \
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.vref_value_11 = 0, \
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.vref_range_11 = 0 \
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} \
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}
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#define OCTEON_EBB7304_CN78XX_DRAM_ODT_1RANK_CONFIGURATION \
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/* 1 */ \
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{ \
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ddr4_dqx_driver_34_ohm, \
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0x00000000ULL, \
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OCTEON_EBB7304_MODEREG_PARAMS1_1RANK_1SLOT, \
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OCTEON_EBB7304_MODEREG_PARAMS2_1RANK_1SLOT, \
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ddr4_rodt_ctl_48_ohm, \
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0x00000000ULL, \
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0 \
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}, \
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/* 2 */ \
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{ \
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ddr4_dqx_driver_34_ohm, \
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0x00000000ULL, \
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OCTEON_EBB7304_MODEREG_PARAMS1_1RANK_2SLOT, \
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OCTEON_EBB7304_MODEREG_PARAMS2_1RANK_2SLOT, \
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ddr4_rodt_ctl_80_ohm, \
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0x00000000ULL, \
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0 \
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}
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#define OCTEON_EBB7304_CN78XX_DRAM_ODT_2RANK_CONFIGURATION \
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/* 1 */ \
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{ \
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ddr4_dqx_driver_34_ohm, \
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0x00000000ULL, \
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OCTEON_EBB7304_MODEREG_PARAMS1_2RANK_1SLOT, \
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OCTEON_EBB7304_MODEREG_PARAMS2_2RANK_1SLOT, \
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ddr4_rodt_ctl_80_ohm, \
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0x00000000ULL, \
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0 \
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}, \
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/* 2 */ \
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{ \
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ddr4_dqx_driver_34_ohm, \
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0x0c0c0303ULL, \
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OCTEON_EBB7304_MODEREG_PARAMS1_2RANK_2SLOT, \
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OCTEON_EBB7304_MODEREG_PARAMS2_2RANK_2SLOT, \
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ddr4_rodt_ctl_48_ohm, \
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0x04080102ULL, \
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0 \
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}
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#define OCTEON_EBB7304_CN78XX_DRAM_ODT_4RANK_CONFIGURATION \
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/* 1 */ \
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{ \
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ddr4_dqx_driver_34_ohm, \
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0x01030203ULL, \
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OCTEON_EBB7304_MODEREG_PARAMS1_4RANK_1SLOT, \
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OCTEON_EBB7304_MODEREG_PARAMS2_4RANK_1SLOT, \
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ddr4_rodt_ctl_48_ohm, \
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0x01010202ULL, \
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0 \
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}
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/*
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* Construct a static initializer for the ddr_configuration_t variable that
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* holds (almost) all of the information required for DDR initialization.
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*/
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/*
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* The parameters below make up the custom_lmc_config data structure.
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* This structure is used to customize the way that the LMC DRAM
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* Controller is configured for a particular board design.
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*
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* Refer to the file lib_octeon_board_table_entry.h for a description
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* of the custom board settings. It is usually kept in the following
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* location... arch/mips/include/asm/arch-octeon/
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*
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*/
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#define OCTEON_EBB7304_DDR_CONFIGURATION \
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/* Interface 0 */ \
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{ \
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.custom_lmc_config = { \
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.min_rtt_nom_idx = 1, \
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.max_rtt_nom_idx = 7, \
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.min_rodt_ctl = 1, \
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.max_rodt_ctl = 7, \
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.ck_ctl = ddr4_driver_34_ohm, \
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.cmd_ctl = ddr4_driver_34_ohm, \
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.ctl_ctl = ddr4_driver_34_ohm, \
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.min_cas_latency = 0, \
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.offset_en = 1, \
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.offset_udimm = 2, \
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.offset_rdimm = 2, \
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.ddr_rtt_nom_auto = 0, \
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.ddr_rodt_ctl_auto = 0, \
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.rlevel_comp_offset_udimm = 0, \
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.rlevel_comp_offset_rdimm = 0, \
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.rlevel_compute = 0, \
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.ddr2t_udimm = 1, \
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.ddr2t_rdimm = 1, \
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.maximum_adjacent_rlevel_delay_increment = 2, \
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.fprch2 = 2, \
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.dll_write_offset = NULL, \
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.dll_read_offset = NULL, \
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.parity = 0 \
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}, \
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.dimm_config_table = { \
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OCTEON_EBB7304_DRAM_SOCKET_CONFIGURATION0, \
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DIMM_CONFIG_TERMINATOR \
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}, \
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.unbuffered = { \
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.ddr_board_delay = 0, \
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.lmc_delay_clk = 0, \
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.lmc_delay_cmd = 0, \
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.lmc_delay_dq = 0 \
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}, \
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.registered = { \
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.ddr_board_delay = 0, \
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.lmc_delay_clk = 0, \
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.lmc_delay_cmd = 0, \
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.lmc_delay_dq = 0 \
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}, \
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.odt_1rank_config = { \
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OCTEON_EBB7304_CN78XX_DRAM_ODT_1RANK_CONFIGURATION \
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}, \
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.odt_2rank_config = { \
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OCTEON_EBB7304_CN78XX_DRAM_ODT_2RANK_CONFIGURATION \
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}, \
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.odt_4rank_config = { \
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OCTEON_EBB7304_CN78XX_DRAM_ODT_4RANK_CONFIGURATION \
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} \
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}, \
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/* Interface 1 */ \
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{ \
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.custom_lmc_config = { \
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.min_rtt_nom_idx = 1, \
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.max_rtt_nom_idx = 7, \
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.min_rodt_ctl = 1, \
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.max_rodt_ctl = 7, \
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.ck_ctl = ddr4_driver_34_ohm, \
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.cmd_ctl = ddr4_driver_34_ohm, \
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.ctl_ctl = ddr4_driver_34_ohm, \
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.min_cas_latency = 0, \
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.offset_en = 1, \
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.offset_udimm = 2, \
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.offset_rdimm = 2, \
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.ddr_rtt_nom_auto = 0, \
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.ddr_rodt_ctl_auto = 0, \
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.rlevel_comp_offset_udimm = 0, \
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.rlevel_comp_offset_rdimm = 0, \
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.rlevel_compute = 0, \
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.ddr2t_udimm = 1, \
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.ddr2t_rdimm = 1, \
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.maximum_adjacent_rlevel_delay_increment = 2, \
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.fprch2 = 2, \
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.dll_write_offset = NULL, \
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.dll_read_offset = NULL, \
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.parity = 0 \
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}, \
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.dimm_config_table = { \
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OCTEON_EBB7304_DRAM_SOCKET_CONFIGURATION1, \
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DIMM_CONFIG_TERMINATOR \
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}, \
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.unbuffered = { \
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.ddr_board_delay = 0, \
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.lmc_delay_clk = 0, \
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.lmc_delay_cmd = 0, \
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.lmc_delay_dq = 0 \
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}, \
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.registered = { \
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.ddr_board_delay = 0, \
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.lmc_delay_clk = 0, \
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.lmc_delay_cmd = 0, \
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|
.lmc_delay_dq = 0 \
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|
}, \
|
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.odt_1rank_config = { \
|
|
OCTEON_EBB7304_CN78XX_DRAM_ODT_1RANK_CONFIGURATION \
|
|
}, \
|
|
.odt_2rank_config = { \
|
|
OCTEON_EBB7304_CN78XX_DRAM_ODT_2RANK_CONFIGURATION \
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|
}, \
|
|
.odt_4rank_config = { \
|
|
OCTEON_EBB7304_CN78XX_DRAM_ODT_4RANK_CONFIGURATION \
|
|
} \
|
|
},
|
|
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#endif /* __BOARD_DDR_H__ */
|