mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
95 lines
2.7 KiB
C
95 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2006 Tensilica, Inc. All Rights Reserved.
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*/
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#ifndef _XTENSA_REGS_H
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#define _XTENSA_REGS_H
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/* Special registers */
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#define IBREAKA 128
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#define DBREAKA 144
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#define DBREAKC 160
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/* Special names for read-only and write-only interrupt registers */
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#define INTREAD 226
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#define INTSET 226
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#define INTCLEAR 227
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/* EXCCAUSE register fields */
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#define EXCCAUSE_EXCCAUSE_SHIFT 0
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#define EXCCAUSE_EXCCAUSE_MASK 0x3F
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#define EXCCAUSE_ILLEGAL_INSTRUCTION 0
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#define EXCCAUSE_SYSTEM_CALL 1
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#define EXCCAUSE_INSTRUCTION_FETCH_ERROR 2
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#define EXCCAUSE_LOAD_STORE_ERROR 3
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#define EXCCAUSE_LEVEL1_INTERRUPT 4
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#define EXCCAUSE_ALLOCA 5
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#define EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6
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#define EXCCAUSE_SPECULATION 7
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#define EXCCAUSE_PRIVILEGED 8
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#define EXCCAUSE_UNALIGNED 9
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#define EXCCAUSE_INSTR_DATA_ERROR 12
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#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13
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#define EXCCAUSE_INSTR_ADDR_ERROR 14
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#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15
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#define EXCCAUSE_ITLB_MISS 16
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#define EXCCAUSE_ITLB_MULTIHIT 17
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#define EXCCAUSE_ITLB_PRIVILEGE 18
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#define EXCCAUSE_ITLB_SIZE_RESTRICTION 19
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#define EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20
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#define EXCCAUSE_DTLB_MISS 24
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#define EXCCAUSE_DTLB_MULTIHIT 25
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#define EXCCAUSE_DTLB_PRIVILEGE 26
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#define EXCCAUSE_DTLB_SIZE_RESTRICTION 27
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#define EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28
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#define EXCCAUSE_STORE_CACHE_ATTRIBUTE 29
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#define EXCCAUSE_COPROCESSOR0_DISABLED 32
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#define EXCCAUSE_COPROCESSOR1_DISABLED 33
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#define EXCCAUSE_COPROCESSOR2_DISABLED 34
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#define EXCCAUSE_COPROCESSOR3_DISABLED 35
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#define EXCCAUSE_COPROCESSOR4_DISABLED 36
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#define EXCCAUSE_COPROCESSOR5_DISABLED 37
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#define EXCCAUSE_COPROCESSOR6_DISABLED 38
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#define EXCCAUSE_COPROCESSOR7_DISABLED 39
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#define EXCCAUSE_LAST 63
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/* PS register fields */
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#define PS_WOE_BIT 18
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#define PS_CALLINC_SHIFT 16
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#define PS_CALLINC_MASK 0x00030000
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#define PS_OWB_SHIFT 8
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#define PS_OWB_MASK 0x00000F00
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#define PS_RING_SHIFT 6
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#define PS_RING_MASK 0x000000C0
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#define PS_UM_BIT 5
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#define PS_EXCM_BIT 4
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#define PS_INTLEVEL_SHIFT 0
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#define PS_INTLEVEL_MASK 0x0000000F
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/* DBREAKCn register fields */
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#define DBREAKC_MASK_BIT 0
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#define DBREAKC_MASK_MASK 0x0000003F
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#define DBREAKC_LOAD_BIT 30
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#define DBREAKC_LOAD_MASK 0x40000000
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#define DBREAKC_STOR_BIT 31
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#define DBREAKC_STOR_MASK 0x80000000
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/* DEBUGCAUSE register fields */
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#define DEBUGCAUSE_DEBUGINT_BIT 5 /* External debug interrupt */
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#define DEBUGCAUSE_BREAKN_BIT 4 /* BREAK.N instruction */
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#define DEBUGCAUSE_BREAK_BIT 3 /* BREAK instruction */
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#define DEBUGCAUSE_DBREAK_BIT 2 /* DBREAK match */
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#define DEBUGCAUSE_IBREAK_BIT 1 /* IBREAK match */
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#define DEBUGCAUSE_ICOUNT_BIT 0 /* ICOUNT would incr. to zero */
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#endif /* _XTENSA_SPECREG_H */
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