mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
211 lines
3.8 KiB
C
211 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2006 Tensilica Inc.
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* Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
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*/
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#ifndef _XTENSA_CACHEASM_H
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#define _XTENSA_CACHEASM_H
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#include <asm/cache.h>
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#include <asm/asmmacro.h>
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#include <linux/stringify.h>
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#define PAGE_SIZE 4096
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#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS)
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#define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)
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#define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
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#define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)
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/*
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* Define cache functions as macros here so that they can be used
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* by the kernel and boot loader. We should consider moving them to a
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* library that can be linked by both.
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*
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* Locking
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*
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* ___unlock_dcache_all
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* ___unlock_icache_all
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*
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* Flush and invaldating
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*
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* ___flush_invalidate_dcache_{all|range|page}
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* ___flush_dcache_{all|range|page}
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* ___invalidate_dcache_{all|range|page}
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* ___invalidate_icache_{all|range|page}
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*
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*/
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.macro __loop_cache_all ar at insn size line_width
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movi \ar, 0
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__loopi \ar, \at, \size, (4 << (\line_width))
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\insn \ar, 0 << (\line_width)
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\insn \ar, 1 << (\line_width)
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\insn \ar, 2 << (\line_width)
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\insn \ar, 3 << (\line_width)
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__endla \ar, \at, 4 << (\line_width)
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.endm
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.macro __loop_cache_range ar as at insn line_width
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extui \at, \ar, 0, \line_width
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add \as, \as, \at
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__loops \ar, \as, \at, \line_width
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\insn \ar, 0
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__endla \ar, \at, (1 << (\line_width))
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.endm
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.macro __loop_cache_page ar at insn line_width
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__loopi \ar, \at, PAGE_SIZE, 4 << (\line_width)
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\insn \ar, 0 << (\line_width)
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\insn \ar, 1 << (\line_width)
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\insn \ar, 2 << (\line_width)
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\insn \ar, 3 << (\line_width)
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__endla \ar, \at, 4 << (\line_width)
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.endm
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.macro ___unlock_dcache_all ar at
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#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE
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__loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
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#endif
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.endm
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.macro ___unlock_icache_all ar at
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#if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE
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__loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH
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#endif
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.endm
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.macro ___flush_invalidate_dcache_all ar at
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#if XCHAL_DCACHE_SIZE
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__loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
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#endif
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.endm
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.macro ___flush_dcache_all ar at
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#if XCHAL_DCACHE_SIZE
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__loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
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#endif
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.endm
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.macro ___invalidate_dcache_all ar at
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#if XCHAL_DCACHE_SIZE
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__loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \
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XCHAL_DCACHE_LINEWIDTH
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#endif
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.endm
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.macro ___invalidate_icache_all ar at
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#if XCHAL_ICACHE_SIZE
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__loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \
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XCHAL_ICACHE_LINEWIDTH
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#endif
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.endm
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.macro ___flush_invalidate_dcache_range ar as at
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#if XCHAL_DCACHE_SIZE
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__loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
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#endif
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.endm
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.macro ___flush_dcache_range ar as at
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#if XCHAL_DCACHE_SIZE
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__loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
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#endif
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.endm
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.macro ___invalidate_dcache_range ar as at
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#if XCHAL_DCACHE_SIZE
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__loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
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#endif
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.endm
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.macro ___invalidate_icache_range ar as at
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#if XCHAL_ICACHE_SIZE
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__loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
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#endif
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.endm
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.macro ___flush_invalidate_dcache_page ar as
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#if XCHAL_DCACHE_SIZE
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__loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
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#endif
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.endm
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.macro ___flush_dcache_page ar as
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#if XCHAL_DCACHE_SIZE
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__loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
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#endif
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.endm
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.macro ___invalidate_dcache_page ar as
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#if XCHAL_DCACHE_SIZE
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__loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH
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#endif
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.endm
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.macro ___invalidate_icache_page ar as
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#if XCHAL_ICACHE_SIZE
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__loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH
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#endif
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.endm
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#endif /* _XTENSA_CACHEASM_H */
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