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https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 15:26:03 +09:00
7e270ec3af
The 'xtfpga' board is actually a set of FPGA evaluation boards that can be configured to run an Xtensa processor. - Avnet Xilinx LX60 - Avnet Xilinx LX110 - Avnet Xilinx LX200 - Xilinx ML605 - Xilinx KC705 These boards share the same components (open-ethernet, ns16550 serial, lcd display, flash, etc.). Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
138 lines
2.8 KiB
Plaintext
138 lines
2.8 KiB
Plaintext
/ {
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compatible = "cdns,xtensa-xtfpga";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&pic>;
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chosen {
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bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x06000000>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "cdns,xtensa-cpu";
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reg = <0>;
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/* Filled in by platform_setup from FPGA register
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* clock-frequency = <100000000>;
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*/
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};
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};
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pic: pic {
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compatible = "cdns,xtensa-pic";
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/* one cell: internal irq number,
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* two cells: second cell == 0: internal irq number
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* second cell == 1: external irq number
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*/
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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clocks {
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osc: main-oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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clk54: clk54 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <54000000>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x00000000 0xf0000000 0x10000000>;
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serial0: serial@0d050020 {
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device_type = "serial";
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compatible = "ns16550a";
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no-loopback-test;
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reg = <0x0d050020 0x20>;
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reg-shift = <2>;
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reg-io-width = <4>;
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native-endian;
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interrupts = <0 1>; /* external irq 0 */
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clocks = <&osc>;
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};
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enet0: ethoc@0d030000 {
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compatible = "opencores,ethoc";
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reg = <0x0d030000 0x4000 0x0d800000 0x4000>;
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native-endian;
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interrupts = <1 1>; /* external irq 1 */
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local-mac-address = [00 50 c2 13 6f 00];
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clocks = <&osc>;
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};
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i2s0: xtfpga-i2s@0d080000 {
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#sound-dai-cells = <0>;
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compatible = "cdns,xtfpga-i2s";
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reg = <0x0d080000 0x40>;
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interrupts = <2 1>; /* external irq 2 */
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clocks = <&cdce706 4>;
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};
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i2c0: i2c-master@0d090000 {
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compatible = "opencores,i2c-ocores";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0d090000 0x20>;
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reg-shift = <2>;
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reg-io-width = <4>;
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native-endian;
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interrupts = <4 1>;
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clocks = <&osc>;
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cdce706: clock-synth@69 {
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compatible = "ti,cdce706";
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#clock-cells = <1>;
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reg = <0x69>;
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clocks = <&clk54>;
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clock-names = "clk_in0";
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};
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};
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spi0: spi-master@0d0a0000 {
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compatible = "cdns,xtfpga-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0d0a0000 0xc>;
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tlv320aic23: sound-codec@0 {
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#sound-dai-cells = <0>;
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compatible = "tlv320aic23";
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reg = <0>;
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spi-max-frequency = <12500000>;
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};
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};
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};
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sound {
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compatible = "simple-audio-card";
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simple-audio-card,format = "i2s";
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simple-audio-card,mclk-fs = <256>;
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simple-audio-card,cpu {
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sound-dai = <&i2s0>;
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};
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simple-audio-card,codec {
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sound-dai = <&tlv320aic23>;
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simple-audio-card,bitclock-master = <0>;
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simple-audio-card,frame-master = <0>;
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clocks = <&cdce706 4>;
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};
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};
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};
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