48 lines
791 B
Plaintext
48 lines
791 B
Plaintext
menu "Xtensa architecture"
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depends on XTENSA
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config SYS_ARCH
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string
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default "xtensa"
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config SYS_CPU
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string "Xtensa Core Variant"
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choice
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prompt "Target select"
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config TARGET_XTFPGA
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bool "Support XTFPGA"
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endchoice
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config SYS_ICACHE_OFF
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bool "Do not enable icache"
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default n
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help
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Do not enable instruction cache in U-Boot.
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config SPL_SYS_ICACHE_OFF
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bool "Do not enable icache in SPL"
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depends on SPL
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default SYS_ICACHE_OFF
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help
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Do not enable instruction cache in SPL.
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config SYS_DCACHE_OFF
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bool "Do not enable dcache"
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default n
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help
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Do not enable data cache in U-Boot.
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config SPL_SYS_DCACHE_OFF
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bool "Do not enable dcache in SPL"
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depends on SPL
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default SYS_DCACHE_OFF
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help
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Do not enable data cache in SPL.
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source "board/cadence/xtfpga/Kconfig"
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endmenu
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