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https://github.com/brain-hackers/u-boot-brain
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f45e747d6d
Newer Intel SoCs have different ways of setting up cache-as-ram (CAR). Add support for these along with suitable configuration options. To make the code cleaner, adjust a few definitions in processor.h so that they can be used from assembler. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
62 lines
1.4 KiB
C
62 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, daniel@omicron.se
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*/
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#ifndef __ASM_PROCESSOR_H_
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#define __ASM_PROCESSOR_H_ 1
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#define X86_GDT_ENTRY_SIZE 8
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#define X86_GDT_ENTRY_NULL 0
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#define X86_GDT_ENTRY_UNUSED 1
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#define X86_GDT_ENTRY_32BIT_CS 2
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#define X86_GDT_ENTRY_32BIT_DS 3
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#define X86_GDT_ENTRY_32BIT_FS 4
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#define X86_GDT_ENTRY_16BIT_CS 5
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#define X86_GDT_ENTRY_16BIT_DS 6
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#define X86_GDT_ENTRY_16BIT_FLAT_CS 7
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#define X86_GDT_ENTRY_16BIT_FLAT_DS 8
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#define X86_GDT_NUM_ENTRIES 9
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#define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE)
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/* Length of the public header on Intel microcode blobs */
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#define UCODE_HEADER_LEN 0x30
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/*
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* This register is documented in (for example) the Intel Atom Processor E3800
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* Product Family Datasheet in "PCU - Power Management Controller (PMC)".
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*
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* RST_CNT: Reset Control Register (RST_CNT) Offset cf9.
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*
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* The naming follows Intel's naming.
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*/
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#define IO_PORT_RESET 0xcf9
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#define SYS_RST (1 << 1) /* 0 for soft reset, 1 for hard reset */
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#define RST_CPU (1 << 2) /* initiate reset */
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#define FULL_RST (1 << 3) /* full power cycle */
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#ifndef __ASSEMBLY__
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static inline __attribute__((always_inline)) void cpu_hlt(void)
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{
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asm("hlt");
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}
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static inline ulong cpu_get_sp(void)
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{
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ulong result;
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asm volatile(
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"mov %%esp, %%eax"
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: "=a" (result));
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return result;
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}
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#endif /* __ASSEMBLY__ */
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#endif
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