mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
77 lines
2.2 KiB
C
77 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
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*/
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/* i8259.h i8259 PIC Registers */
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#ifndef _ASMI386_I8259_H_
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#define _ASMI386_I8959_H_
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/* PIC I/O mapped registers */
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#define IRR 0x0 /* Interrupt Request Register */
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#define ISR 0x0 /* In-Service Register */
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#define ICW1 0x0 /* Initialization Control Word 1 */
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#define OCW2 0x0 /* Operation Control Word 2 */
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#define OCW3 0x0 /* Operation Control Word 3 */
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#define ICW2 0x1 /* Initialization Control Word 2 */
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#define ICW3 0x1 /* Initialization Control Word 3 */
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#define ICW4 0x1 /* Initialization Control Word 4 */
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#define IMR 0x1 /* Interrupt Mask Register */
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/* IRR, IMR, ISR and ICW3 bits */
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#define IR7 0x80 /* IR7 */
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#define IR6 0x40 /* IR6 */
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#define IR5 0x20 /* IR5 */
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#define IR4 0x10 /* IR4 */
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#define IR3 0x08 /* IR3 */
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#define IR2 0x04 /* IR2 */
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#define IR1 0x02 /* IR1 */
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#define IR0 0x01 /* IR0 */
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/* SEOI bits */
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#define SEOI_IR7 0x07 /* IR7 */
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#define SEOI_IR6 0x06 /* IR6 */
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#define SEOI_IR5 0x05 /* IR5 */
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#define SEOI_IR4 0x04 /* IR4 */
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#define SEOI_IR3 0x03 /* IR3 */
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#define SEOI_IR2 0x02 /* IR2 */
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#define SEOI_IR1 0x01 /* IR1 */
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#define SEOI_IR0 0x00 /* IR0 */
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/* OCW2 bits */
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#define OCW2_RCLR 0x00 /* Rotate/clear */
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#define OCW2_NEOI 0x20 /* Non specific EOI */
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#define OCW2_NOP 0x40 /* NOP */
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#define OCW2_SEOI 0x60 /* Specific EOI */
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#define OCW2_RSET 0x80 /* Rotate/set */
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#define OCW2_REOI 0xa0 /* Rotate on non specific EOI */
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#define OCW2_PSET 0xc0 /* Priority Set Command */
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#define OCW2_RSEOI 0xe0 /* Rotate on specific EOI */
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/* ICW1 bits */
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#define ICW1_SEL 0x10 /* Select ICW1 */
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#define ICW1_LTIM 0x08 /* Level-Triggered Interrupt Mode */
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#define ICW1_ADI 0x04 /* Address Interval */
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#define ICW1_SNGL 0x02 /* Single PIC */
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#define ICW1_EICW4 0x01 /* Expect initilization ICW4 */
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/*
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* ICW2 is the starting vector number
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*
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* ICW2 is bit-mask of present slaves for a master device,
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* or the slave ID for a slave device
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*/
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/* ICW4 bits */
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#define ICW4_AEOI 0x02 /* Automatic EOI Mode */
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#define ICW4_PM 0x01 /* Microprocessor Mode */
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#define ELCR1 0x4d0
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#define ELCR2 0x4d1
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int i8259_init(void);
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#endif /* _ASMI386_I8959_H_ */
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