mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 15:26:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
188 lines
4.1 KiB
C
188 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2008 Renesas Solutions Corp.
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*
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* SH7723 Internal I/O register
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*/
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#ifndef _ASM_CPU_SH7723_H_
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#define _ASM_CPU_SH7723_H_
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#define CACHE_OC_NUM_WAYS 4
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#define CCR_CACHE_INIT 0x0000090d
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/* EXP */
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#define TRA 0xFF000020
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#define EXPEVT 0xFF000024
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#define INTEVT 0xFF000028
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/* MMU */
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#define PTEH 0xFF000000
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#define PTEL 0xFF000004
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#define TTB 0xFF000008
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#define TEA 0xFF00000C
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#define MMUCR 0xFF000010
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#define PASCR 0xFF000070
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#define IRMCR 0xFF000078
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/* CACHE */
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#define CCR 0xFF00001C
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#define RAMCR 0xFF000074
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/* INTC */
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/* BSC */
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#define CMNCR 0xFEC10000
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#define CS0BCR 0xFEC10004
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#define CS2BCR 0xFEC10008
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#define CS4BCR 0xFEC10010
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#define CS5ABCR 0xFEC10014
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#define CS5BBCR 0xFEC10018
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#define CS6ABCR 0xFEC1001C
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#define CS6BBCR 0xFEC10020
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#define CS0WCR 0xFEC10024
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#define CS2WCR 0xFEC10028
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#define CS4WCR 0xFEC10030
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#define CS5AWCR 0xFEC10034
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#define CS5BWCR 0xFEC10038
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#define CS6AWCR 0xFEC1003C
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#define CS6BWCR 0xFEC10040
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#define RBWTCNT 0xFEC10054
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/* SBSC */
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#define SBSC_SDCR 0xFE400008
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#define SBSC_SDWCR 0xFE40000C
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#define SBSC_SDPCR 0xFE400010
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#define SBSC_RTCSR 0xFE400014
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#define SBSC_RTCNT 0xFE400018
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#define SBSC_RTCOR 0xFE40001C
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#define SBSC_RFCR 0xFE400020
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/* DMAC */
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/* CPG */
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#define FRQCR 0xA4150000
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#define VCLKCR 0xA4150004
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#define SCLKACR 0xA4150008
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#define SCLKBCR 0xA415000C
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#define IRDACLKCR 0xA4150018
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#define PLLCR 0xA4150024
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#define DLLFRQ 0xA4150050
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/* LOW POWER MODE */
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#define STBCR 0xA4150020
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#define MSTPCR0 0xA4150030
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#define MSTPCR1 0xA4150034
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#define MSTPCR2 0xA4150038
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/* RWDT */
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#define RWTCNT 0xA4520000
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#define RWTCSR 0xA4520004
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#define WTCNT RWTCNT
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/* TMU */
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#define TMU_BASE 0xFFD80000
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/* TPU */
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/* CMT */
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#define CMSTR 0xA44A0000
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#define CMCSR 0xA44A0060
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#define CMCNT 0xA44A0064
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#define CMCOR 0xA44A0068
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/* MSIOF */
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/* SCIF */
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#define SCIF0_BASE 0xFFE00000
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#define SCIF1_BASE 0xFFE10000
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#define SCIF2_BASE 0xFFE20000
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#define SCIF3_BASE 0xa4e30000
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#define SCIF4_BASE 0xa4e40000
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#define SCIF5_BASE 0xa4e50000
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/* RTC */
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/* IrDA */
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/* KEYSC */
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/* USB */
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/* IIC */
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/* FLCTL */
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/* VPU */
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/* VIO(CEU) */
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/* VIO(VEU) */
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/* VIO(BEU) */
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/* 2DG */
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/* LCDC */
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/* VOU */
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/* TSIF */
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/* SIU */
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/* ATAPI */
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/* PFC */
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#define PACR 0xA4050100
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#define PBCR 0xA4050102
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#define PCCR 0xA4050104
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#define PDCR 0xA4050106
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#define PECR 0xA4050108
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#define PFCR 0xA405010A
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#define PGCR 0xA405010C
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#define PHCR 0xA405010E
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#define PJCR 0xA4050110
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#define PKCR 0xA4050112
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#define PLCR 0xA4050114
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#define PMCR 0xA4050116
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#define PNCR 0xA4050118
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#define PQCR 0xA405011A
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#define PRCR 0xA405011C
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#define PSCR 0xA405011E
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#define PTCR 0xA4050140
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#define PUCR 0xA4050142
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#define PVCR 0xA4050144
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#define PWCR 0xA4050146
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#define PXCR 0xA4050148
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#define PYCR 0xA405014A
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#define PZCR 0xA405014C
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#define PSELA 0xA405014E
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#define PSELB 0xA4050150
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#define PSELC 0xA4050152
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#define PSELD 0xA4050154
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#define HIZCRA 0xA4050158
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#define HIZCRB 0xA405015A
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#define HIZCRC 0xA405015C
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#define HIZCRD 0xA405015E
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#define MSELCRA 0xA4050180
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#define MSELCRB 0xA4050182
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#define PULCR 0xA4050184
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#define DRVCRA 0xA405018A
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#define DRVCRB 0xA405018C
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/* I/O Port */
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#define PADR 0xA4050120
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#define PBDR 0xA4050122
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#define PCDR 0xA4050124
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#define PDDR 0xA4050126
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#define PEDR 0xA4050128
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#define PFDR 0xA405012A
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#define PGDR 0xA405012C
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#define PHDR 0xA405012E
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#define PJDR 0xA4050130
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#define PKDR 0xA4050132
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#define PLDR 0xA4050134
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#define PMDR 0xA4050136
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#define PNDR 0xA4050138
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#define PQDR 0xA405013A
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#define PRDR 0xA405013C
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#define PSDR 0xA405013E
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#define PTDR 0xA4050160
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#define PUDR 0xA4050162
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#define PVDR 0xA4050164
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#define PWDR 0xA4050166
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#define PXDR 0xA4050168
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#define PYDR 0xA405016A
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#define PZDR 0xA405016C
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/* UBC */
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/* H-UDI */
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#endif /* _ASM_CPU_SH7723_H_ */
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