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https://github.com/brain-hackers/u-boot-brain
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a6d7e8c914
At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to
control the enabling of SiFive CLINT support in both SPL (M-mode)
and U-Boot proper (S-mode). So for a typical SPL config that the
SiFive CLINT driver is enabled in both SPL and U-Boot proper, that
means the S-mode U-Boot tries to access the memory-mapped CLINT
registers directly, instead of the normal 'rdtime' instruction.
This was not a problem before, as the hardware does not forbid the
access from S-mode. However this becomes an issue now with OpenSBI
commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain")
that the SiFive CLINT register space is protected by PMP for M-mode
access only. U-Boot proper does not boot any more with the latest
OpenSBI, that access exceptions are fired forever from U-Boot when
trying to read the timer value via the SiFive CLINT driver in U-Boot.
To solve this, we need to split current SiFive CLINT support between
SPL and U-Boot proper, using 2 separate Kconfig options.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
49 lines
1.1 KiB
C
49 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (c) 2017 Microsemi Corporation.
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* Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
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*/
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#ifndef __ASM_GBL_DATA_H
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#define __ASM_GBL_DATA_H
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#include <asm/smp.h>
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#include <asm/u-boot.h>
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#include <compiler.h>
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/* Architecture-specific global data */
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struct arch_global_data {
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long boot_hart; /* boot hart id */
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phys_addr_t firmware_fdt_addr;
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#if CONFIG_IS_ENABLED(SIFIVE_CLINT)
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void __iomem *clint; /* clint base address */
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#endif
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#ifdef CONFIG_ANDES_PLIC
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void __iomem *plic; /* plic base address */
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#endif
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#if CONFIG_IS_ENABLED(SMP)
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struct ipi_data ipi[CONFIG_NR_CPUS];
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#endif
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#ifndef CONFIG_XIP
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ulong available_harts;
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#endif
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};
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#include <asm-generic/global_data.h>
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#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("gp")
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static inline void set_gd(volatile gd_t *gd_ptr)
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{
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#ifdef CONFIG_64BIT
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asm volatile("ld gp, %0\n" : : "m"(gd_ptr));
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#else
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asm volatile("lw gp, %0\n" : : "m"(gd_ptr));
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#endif
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}
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#endif /* __ASM_GBL_DATA_H */
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