mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 15:26:03 +09:00
2113c0045c
Add dts support for fu740. The HiFive Unmatched support is based on fu740 cpu and drivers in following patch set. Signed-off-by: Green Wan <green.wan@sifive.com> [greentime.hu: set fu740 speed to 1.2GHz] Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
106 lines
2.1 KiB
Plaintext
106 lines
2.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
|
/*
|
|
* (C) Copyright 2020-2021 SiFive, Inc
|
|
*/
|
|
|
|
#include <dt-bindings/reset/sifive-fu740-prci.h>
|
|
|
|
/ {
|
|
cpus {
|
|
assigned-clocks = <&prci PRCI_CLK_COREPLL>;
|
|
assigned-clock-rates = <1200000000>;
|
|
u-boot,dm-spl;
|
|
cpu0: cpu@0 {
|
|
clocks = <&prci PRCI_CLK_COREPLL>;
|
|
u-boot,dm-spl;
|
|
status = "okay";
|
|
cpu0_intc: interrupt-controller {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
cpu1: cpu@1 {
|
|
clocks = <&prci PRCI_CLK_COREPLL>;
|
|
u-boot,dm-spl;
|
|
cpu1_intc: interrupt-controller {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
cpu2: cpu@2 {
|
|
clocks = <&prci PRCI_CLK_COREPLL>;
|
|
u-boot,dm-spl;
|
|
cpu2_intc: interrupt-controller {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
cpu3: cpu@3 {
|
|
clocks = <&prci PRCI_CLK_COREPLL>;
|
|
u-boot,dm-spl;
|
|
cpu3_intc: interrupt-controller {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
cpu4: cpu@4 {
|
|
clocks = <&prci PRCI_CLK_COREPLL>;
|
|
u-boot,dm-spl;
|
|
cpu4_intc: interrupt-controller {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
};
|
|
|
|
soc {
|
|
u-boot,dm-spl;
|
|
clint: clint@2000000 {
|
|
compatible = "riscv,clint0";
|
|
interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
|
|
&cpu1_intc 3 &cpu1_intc 7
|
|
&cpu2_intc 3 &cpu2_intc 7
|
|
&cpu3_intc 3 &cpu3_intc 7
|
|
&cpu4_intc 3 &cpu4_intc 7>;
|
|
reg = <0x0 0x2000000 0x0 0x10000>;
|
|
u-boot,dm-spl;
|
|
};
|
|
prci: clock-controller@10000000 {
|
|
#reset-cells = <1>;
|
|
resets = <&prci PRCI_RST_DDR_CTRL_N>,
|
|
<&prci PRCI_RST_DDR_AXI_N>,
|
|
<&prci PRCI_RST_DDR_AHB_N>,
|
|
<&prci PRCI_RST_DDR_PHY_N>,
|
|
<&prci PRCI_RST_GEMGXL_N>,
|
|
<&prci PRCI_RST_CLTX_N>;
|
|
reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb",
|
|
"ddr_phy", "gemgxl_reset", "cltx_reset";
|
|
};
|
|
dmc: dmc@100b0000 {
|
|
compatible = "sifive,fu740-c000-ddr";
|
|
reg = <0x0 0x100b0000 0x0 0x0800
|
|
0x0 0x100b2000 0x0 0x2000
|
|
0x0 0x100b8000 0x0 0x1000>;
|
|
clocks = <&prci PRCI_CLK_DDRPLL>;
|
|
clock-frequency = <933333324>;
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
};
|
|
|
|
&prci {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&uart0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&spi0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
ð0 {
|
|
assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
|
|
assigned-clock-rates = <125125000>;
|
|
};
|
|
|
|
&ccache {
|
|
status = "okay";
|
|
};
|