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https://github.com/brain-hackers/u-boot-brain
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3a25db1753
When two FMan's are present on a board, the MDIO nodes are found at the same offsets inside each FMan. This causes "non unique device name" errors when registering the MDIO nodes under the second FMan. Fix this by updating the offsets of the MDIO nodes to include the parent FMan's offset. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
173 lines
2.7 KiB
Plaintext
173 lines
2.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* T4240RDB Device Tree Source
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*
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* Copyright 2013 - 2015 Freescale Semiconductor Inc.
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* Copyright 2019-2021 NXP
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*/
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/include/ "t4240.dtsi"
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/ {
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model = "fsl,T4240RDB";
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compatible = "fsl,T4240RDB";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases {
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spi0 = &espi0;
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};
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};
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&soc {
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fman@400000 {
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ethernet@e0000 {
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phy-handle = <&sgmiiphy21>;
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phy-connection-type = "sgmii";
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};
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ethernet@e2000 {
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phy-handle = <&sgmiiphy22>;
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phy-connection-type = "sgmii";
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};
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ethernet@e4000 {
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phy-handle = <&sgmiiphy23>;
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phy-connection-type = "sgmii";
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};
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ethernet@e6000 {
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phy-handle = <&sgmiiphy24>;
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phy-connection-type = "sgmii";
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};
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ethernet@e8000 {
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status = "disabled";
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};
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ethernet@ea000 {
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status = "disabled";
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};
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ethernet@f0000 {
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phy-handle = <&xfiphy1>;
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phy-connection-type = "xgmii";
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};
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ethernet@f2000 {
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phy-handle = <&xfiphy2>;
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phy-connection-type = "xgmii";
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};
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};
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fman@500000 {
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ethernet@e0000 {
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phy-handle = <&sgmiiphy41>;
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phy-connection-type = "sgmii";
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};
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ethernet@e2000 {
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phy-handle = <&sgmiiphy42>;
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phy-connection-type = "sgmii";
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};
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ethernet@e4000 {
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phy-handle = <&sgmiiphy43>;
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phy-connection-type = "sgmii";
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};
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ethernet@e6000 {
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phy-handle = <&sgmiiphy44>;
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phy-connection-type = "sgmii";
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};
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ethernet@e8000 {
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status = "disabled";
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};
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ethernet@ea000 {
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status = "disabled";
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};
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ethernet@f0000 {
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phy-handle = <&xfiphy3>;
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phy-connection-type = "xgmii";
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};
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ethernet@f2000 {
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phy-handle = <&xfiphy4>;
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phy-connection-type = "xgmii";
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};
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mdio@5fc000 {
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sgmiiphy21: ethernet-phy@0 {
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reg = <0x0>;
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};
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sgmiiphy22: ethernet-phy@1 {
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reg = <0x1>;
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};
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sgmiiphy23: ethernet-phy@2 {
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reg = <0x2>;
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};
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sgmiiphy24: ethernet-phy@3 {
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reg = <0x3>;
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};
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sgmiiphy41: ethernet-phy@4 {
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reg = <0x4>;
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};
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sgmiiphy42: ethernet-phy@5 {
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reg = <0x5>;
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};
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sgmiiphy43: ethernet-phy@6 {
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reg = <0x6>;
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};
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sgmiiphy44: ethernet-phy@7 {
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reg = <0x7>;
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};
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};
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mdio@5fd000 {
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xfiphy1: ethernet-phy@10 {
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compatible = "ethernet-phy-id13e5.1002";
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reg = <0x10>;
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};
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xfiphy2: ethernet-phy@11 {
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compatible = "ethernet-phy-id13e5.1002";
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reg = <0x11>;
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};
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xfiphy3: ethernet-phy@13 {
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compatible = "ethernet-phy-id13e5.1002";
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reg = <0x13>;
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};
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xfiphy4: ethernet-phy@12 {
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compatible = "ethernet-phy-id13e5.1002";
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reg = <0x12>;
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};
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};
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};
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};
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&espi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-max-frequency = <10000000>; /* input clock */
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};
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};
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/include/ "t4240si-post.dtsi"
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