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https://github.com/brain-hackers/u-boot-brain
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9ec8a585f4
Add ESPI slave node for T1024RDB. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
82 lines
1.5 KiB
Plaintext
82 lines
1.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* T1024RDB Device Tree Source
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*
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* Copyright 2013 - 2015 Freescale Semiconductor Inc.
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* Copyright 2019-2020 NXP
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*/
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/include/ "t102x.dtsi"
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/ {
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model = "fsl,T1024RDB";
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compatible = "fsl,T1024RDB";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases {
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sg_2500_aqr105_phy4 = &sg_2500_aqr105_phy4;
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spi0 = &espi0;
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};
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soc: soc@ffe000000 {
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
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reg = <0xf 0xfe000000 0 0x00001000>;
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fman@400000 {
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fm1mac1: ethernet@e0000 {
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phy-handle = <&xg_aqr105_phy3>;
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phy-connection-type = "xgmii";
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};
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fm1mac2: ethernet@e2000 {
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};
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fm1mac3: ethernet@e4000 {
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phy-handle = <&rgmii_phy2>;
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phy-connection-type = "rgmii";
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};
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fm1mac4: ethernet@e6000 {
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phy-handle = <&rgmii_phy1>;
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phy-connection-type = "rgmii";
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};
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mdio0: mdio@fc000 {
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rgmii_phy1: ethernet-phy@2 {
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reg = <0x2>;
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};
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rgmii_phy2: ethernet-phy@6 {
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reg = <0x6>;
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};
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};
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xmdio0: mdio@fd000 {
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xg_aqr105_phy3: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x1>;
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};
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sg_2500_aqr105_phy4: ethernet-phy@2 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x2>;
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};
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};
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};
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};
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};
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&espi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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/* input clock */
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spi-max-frequency = <10000000>;
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};
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};
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#include "t1024si-post.dtsi"
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