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https://github.com/brain-hackers/u-boot-brain
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e6e00b4c59
Add ESPI slave node for P3041DS. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
159 lines
3.1 KiB
Plaintext
159 lines
3.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* P3041DS Device Tree Source
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*
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* Copyright 2010 - 2015 Freescale Semiconductor Inc.
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* Copyright 2019-2020 NXP
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*/
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/include/ "p3041.dtsi"
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/ {
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model = "fsl,P3041DS";
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compatible = "fsl,P3041DS";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases{
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phy_rgmii_0 = &phy_rgmii_0;
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phy_rgmii_1 = &phy_rgmii_1;
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phy_sgmii_1c = &phy_sgmii_1c;
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phy_sgmii_1d = &phy_sgmii_1d;
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phy_sgmii_1e = &phy_sgmii_1e;
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phy_sgmii_1f = &phy_sgmii_1f;
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phy_xgmii_1 = &phy_xgmii_1;
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phy_xgmii_2 = &phy_xgmii_2;
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emi1_rgmii = &hydra_mdio_rgmii;
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emi1_sgmii = &hydra_mdio_sgmii;
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emi2_xgmii = &hydra_mdio_xgmii;
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spi0 = &espi0;
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};
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soc: soc@ffe000000 {
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
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reg = <0xf 0xfe000000 0 0x00001000>;
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fman@400000{
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ethernet@e0000 {
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phy-handle = <&phy_sgmii_1c>;
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phy-connection-type = "sgmii";
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};
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ethernet@e2000 {
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phy-handle = <&phy_sgmii_1d>;
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phy-connection-type = "sgmii";
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};
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ethernet@e4000 {
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phy-handle = <&phy_sgmii_1e>;
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phy-connection-type = "sgmii";
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};
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ethernet@e6000 {
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phy-handle = <&phy_sgmii_1f>;
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phy-connection-type = "sgmii";
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};
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ethernet@e8000 {
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phy-handle = <&phy_rgmii_1>;
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phy-connection-type = "rgmii";
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};
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ethernet@f0000 {
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phy-handle = <&phy_xgmii_1>;
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phy-connection-type = "xgmii";
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};
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hydra_mdio_xgmii: mdio@f1000 {
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status = "disabled";
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phy_xgmii_1: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x4>;
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};
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phy_xgmii_2: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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};
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};
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};
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};
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lbc: localbus@ffe124000 {
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reg = <0xf 0xfe124000 0 0x1000>;
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ranges = <0 0 0xf 0xe8000000 0x08000000
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2 0 0xf 0xffa00000 0x00040000
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3 0 0xf 0xffdf0000 0x00008000>;
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board-control@3,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";
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reg = <3 0 0x30>;
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ranges = <0 3 0 0x30>;
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mdio-mux-emi1 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mdio-mux-mmioreg", "mdio-mux";
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mdio-parent-bus = <&mdio0>;
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reg = <9 1>;
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mux-mask = <0x78>;
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hydra_mdio_rgmii: rgmii-mdio@8 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <8>;
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status = "disabled";
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phy_rgmii_0: ethernet-phy@0 {
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reg = <0x0>;
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};
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phy_rgmii_1: ethernet-phy@1 {
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reg = <0x1>;
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};
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};
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hydra_mdio_sgmii: sgmii-mdio@28 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x28>;
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status = "disabled";
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phy_sgmii_1c: ethernet-phy@1c {
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reg = <0x1c>;
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};
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phy_sgmii_1d: ethernet-phy@1d {
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reg = <0x1d>;
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};
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phy_sgmii_1e: ethernet-phy@1e {
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reg = <0x1e>;
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};
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phy_sgmii_1f: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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};
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};
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};
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};
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&espi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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/* input clock */
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spi-max-frequency = <10000000>;
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};
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};
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/include/ "p3041si-post.dtsi"
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