mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
247921f966
P1020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
52 lines
1.2 KiB
Plaintext
52 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* P1020RDB-PC (36-bit address map) Device Tree Source
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*
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* Copyright 2013 - 2015 Freescale Semiconductor Inc.
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* Copyright 2019 NXP
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*/
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/include/ "p1020.dtsi"
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/ {
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model = "fsl,P1020RDB-PC";
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compatible = "fsl,P1020RDB-PC";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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soc: soc@fffe00000 {
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ranges = <0x0 0xf 0xffe00000 0x100000>;
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};
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pci1: pcie@fffe09000 {
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reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */
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ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000 /* downstream I/O */
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0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
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};
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pci0: pcie@fffe0a000 {
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reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */
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ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */
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0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
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};
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aliases {
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spi0 = &espi0;
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};
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};
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/include/ "p1020rdb-pc.dtsi"
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/include/ "p1020-post.dtsi"
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&espi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-max-frequency = <10000000>; /* input clock */
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};
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};
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