mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
247921f966
P1020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
95 lines
1.9 KiB
Plaintext
95 lines
1.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* P1020 Silicon/SoC Device Tree Source (post include)
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*
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* Copyright 2013 Freescale Semiconductor Inc.
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* Copyright 2019 NXP
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*/
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,p1020-immr", "simple-bus";
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bus-frequency = <0x0>;
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usb@22000 {
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compatible = "fsl-usb2-dr";
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reg = <0x22000 0x1000>;
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phy_type = "ulpi";
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};
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usb@23000 {
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compatible = "fsl-usb2-dr";
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reg = <0x23000 0x1000>;
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phy_type = "ulpi";
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <4>;
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reg = <0x40000 0x40000>;
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compatible = "fsl,mpic";
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device_type = "open-pic";
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big-endian;
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single-cpu-affinity;
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last-interrupt-source = <255>;
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};
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esdhc: esdhc@2e000 {
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compatible = "fsl,esdhc";
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reg = <0x2e000 0x1000>;
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/* Filled in by U-Boot */
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clock-frequency = <0>;
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};
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espi0: spi@7000 {
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compatible = "fsl,mpc8536-espi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x7000 0x1000>;
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fsl,espi-num-chipselects = <4>;
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status = "disabled";
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};
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/include/ "pq3-i2c-0.dtsi"
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/include/ "pq3-i2c-1.dtsi"
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/include/ "pq3-etsec2-0.dtsi"
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enet0: enet0_grp2: ethernet@b0000 {
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};
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/include/ "pq3-etsec2-1.dtsi"
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enet1: enet1_grp2: ethernet@b1000 {
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};
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/include/ "pq3-etsec2-2.dtsi"
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enet2: enet2_grp2: ethernet@b2000 {
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};
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};
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/include/ "pq3-etsec2-grp2-0.dtsi"
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/include/ "pq3-etsec2-grp2-1.dtsi"
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/include/ "pq3-etsec2-grp2-2.dtsi"
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/* PCIe controller base address 0x9000 */
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&pci1 {
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compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
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law_trgt_if = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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};
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/* PCIe controller base address 0xa000 */
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&pci0 {
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compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
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law_trgt_if = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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};
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