mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
5d57dfad3f
As the ownership is now Hitachi Power Grids, change the license string and adapt the compatible string in DTS files. For kmeter1.dts we change it to "keymile,KMETER1" for now, as this is then compliant with what is submitted to the linux kernel. All other boards don't have a upstreamed version in linux mainline. Signed-off-by: Holger Brunck <holger.brunck@hitachi-powergrids.com> CC: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com> CC: Heiko Schocher <hs@denx.de> CC: Marek Vasut <marex@denx.de> CC: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
393 lines
8.0 KiB
Plaintext
393 lines
8.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Hitachi Power Grids TEGR1 Device Tree Source
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*
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* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
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*
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*/
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/dts-v1/;
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/ {
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model = "KMTEGR1";
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compatible = "hitachi,kmpbec8309";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet_zynq;
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ethernet1 = &enet_piggy2;
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serial0 = &serial0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8309@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <16384>; // L1, 16K
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i-cache-size = <16384>; // L1, 16K
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timebase-frequency = <66000000>;
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bus-frequency = <264000000>;
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clock-frequency = <264000000>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x10000000>;
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};
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soc: soc8309@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x0 0xe0000000 0x00100000>;
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reg = <0xe0000000 0x00000200>;
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bus-frequency = <264000000>;
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl,mpc8313-i2c","fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <14 0x8>;
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interrupt-parent = <&ipic>;
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clock-frequency = <400000>;
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mux@70 {
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compatible = "nxp,pca9547";
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reg = <0x70>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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/*
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* Inventory EEPROM of the
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* unit itself
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*/
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ivm@50 {
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label = "MAIN_CTRL";
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compatible = "dummy";
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reg = <0x50>;
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};
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};
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i2c@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* Temperature sensors */
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temp@48 {
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label = "front";
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compatible = "national,lm75";
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reg = <0x48>;
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};
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temp@49 {
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label = "board";
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compatible = "national,lm75";
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reg = <0x49>;
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};
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temp@4a {
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label = "power";
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compatible = "national,lm75";
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reg = <0x4a>;
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};
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temp@4b {
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label = "bottom";
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compatible = "national,lm75";
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reg = <0x4b>;
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};
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};
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i2c@6 {
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reg = <6>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c@5 {
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reg = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c@7 {
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reg = <7>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c@3 {
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reg = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <264000000>;
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interrupts = <9 0x8>;
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interrupt-parent = <&ipic>;
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};
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dma@82a8 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8309-dma", "fsl,elo-dma";
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reg = <0x82a8 4>;
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ranges = <0 0x8100 0x1a8>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8309-dma-channel",
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"fsl,elo-dma-channel";
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reg = <0 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8309-dma-channel",
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"fsl,elo-dma-channel";
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reg = <0x80 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8309-dma-channel",
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"fsl,elo-dma-channel";
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reg = <0x100 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8309-dma-channel",
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"fsl,elo-dma-channel";
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reg = <0x180 0x28>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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};
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ipic: pic@700 {
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#address-cells = <0>;
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#interrupt-cells = <2>;
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compatible = "fsl,pq2pro-pic", "fsl,ipic";
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interrupt-controller;
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reg = <0x700 0x100>;
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device_type = "ipic";
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};
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gpio1: gpio-controller@c00 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
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reg = <0xc00 0x100>;
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interrupts = <75 0x8>;
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interrupt-parent = <&ipic>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio-controller@d00 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
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reg = <0xd00 0x100>;
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interrupts = <75 0x8>;
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interrupt-parent = <&ipic>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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spi@7000 {
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cell-index = <0>;
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compatible = "fsl,spi";
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reg = <0x7000 0x1000>;
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interrupts = <16 0x8>;
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interrupt-parent = <&ipic>;
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mode = "cpu";
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#address-cells = <1>;
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#size-cells = <0>;
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/* GPIO_15 chipselect for ZYNQ flash */
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gpios = <&gpio1 15 0>;
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zynq_flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spansion,m25p80";
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reg = <0>;
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spi-max-frequency = <4000000>;
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m25p,fast-read;
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partition@0 {
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label = "bootloader";
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reg = <0x0 0x01000000>;
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};
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};
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};
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};
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qe: qe@e0100000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "qe";
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compatible = "fsl,qe";
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ranges = <0x0 0xe0100000 0x00100000>;
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reg = <0xe0100000 0x480>;
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brg-frequency = <0>;
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bus-frequency = <396000000>;
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fsl,qe-num-snums = <32>;
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muram@10000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,qe-muram", "fsl,cpm-muram";
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ranges = <0x0 0x00010000 0x00004000>;
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data-only@0 {
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compatible = "fsl,qe-muram-data",
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"fsl,cpm-muram-data";
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reg = <0x0 0x4000>;
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};
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};
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/* ZYNQ (UCC1, MDIO 0x10, MII) */
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enet_zynq: ethernet@2000 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <1>;
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reg = <0x2000 0x200>;
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interrupts = <32>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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/*id=0, full-dup, 100M, no-pause, no-asym_p*/
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fixed-link = <0 1 100 0 0>;
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rx-clock-name = "clk9";
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tx-clock-name = "clk10";
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phy-connection-type = "mii";
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};
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/* Piggy2 (UCC3, MDIO 0x00, RMII) */
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enet_piggy2: ucc@2200 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <3>;
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reg = <0x2200 0x200>;
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interrupts = <34>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk12";
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phy-handle = <&phy_piggy2>;
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phy-connection-type = "rmii";
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};
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mdio@2320 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2320 0x38>;
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compatible = "fsl,ucc-mdio";
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/* Piggy2 (UCC3, MDIO 0x00, RMII) */
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phy_piggy2: ethernet-phy@0 {
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reg = <0x0>;
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device_type = "ethernet-phy";
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};
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/* Explicitly set the tbi-phy to a non-zero address
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* so that it does not conflict with phy_piggy2 that
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* is unfortunately at address 0
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*/
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tbi1: tbi-phy@1 {
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reg = <0x1>;
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device_type = "tbi-phy";
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};
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};
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qeic: interrupt-controller@80 {
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interrupt-controller;
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compatible = "fsl,qe-ic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x80 0x80>;
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big-endian;
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interrupts = <32 8 33 8>;
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interrupt-parent = <&ipic>;
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};
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bootcount@0x13ff8 {
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device_type = "bootcount";
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compatible = "u-boot,bootcount";
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reg = <0x13ff8 0x08>;
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};
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};
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localbus@e0005000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc8309-localbus", "fsl,pq2pro-localbus",
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"simple-bus";
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reg = <0xe0005000 0xd8>;
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ranges = <0 0 0xf0000000 0x04000000
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1 0 0xe8000000 0x01000000
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2 0 0xe0000000 0x10000000
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3 0 0xb0000000 0x10000000>;
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flash@0,0 {
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compatible = "cfi-flash";
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reg = <0 0x00000000 0x04000000>;
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bank-width = <2>;
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nornand = "nor";
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#address-cells = <1>;
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#size-cells = <1>;
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use-advanced-sector-protection;
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partition@0 { /* 768KB */
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label = "u-boot";
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reg = <0 0xc0000>;
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};
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partition@c0000 { /* 256KB */
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label = "qe-fw";
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reg = <0xc0000 0x40000>;
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};
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partition@100000 { /* 128KB */
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label = "env";
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reg = <0x100000 0x20000>;
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};
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partition@120000 { /* 128KB */
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label = "envred";
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reg = <0x120000 0x20000>;
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};
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partition@140000 { /* 64256KB */
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label = "ubi0";
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reg = <0x140000 0x3EC0000>;
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};
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};
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};
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};
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#include "km8309-uboot.dtsi"
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