mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
64 lines
1.7 KiB
C
64 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2011 Andes Technology Corporation
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* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*/
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#ifndef _ASM_CACHE_H
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#define _ASM_CACHE_H
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/* cache */
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int icache_status(void);
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void icache_enable(void);
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void icache_disable(void);
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int dcache_status(void);
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void dcache_enable(void);
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void dcache_disable(void);
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void cache_flush(void);
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#define DEFINE_GET_SYS_REG(reg) \
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static inline unsigned long GET_##reg(void) \
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{ \
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unsigned long val; \
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__asm__ volatile ( \
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"mfsr %0, $"#reg : "=&r" (val) : : "memory" \
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); \
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return val; \
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}
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enum cache_t {ICACHE, DCACHE};
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DEFINE_GET_SYS_REG(ICM_CFG);
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DEFINE_GET_SYS_REG(DCM_CFG);
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/* I-cache sets (# of cache lines) per way */
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#define ICM_CFG_OFF_ISET 0
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/* I-cache ways */
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#define ICM_CFG_OFF_IWAY 3
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#define ICM_CFG_MSK_ISET (0x7 << ICM_CFG_OFF_ISET)
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#define ICM_CFG_MSK_IWAY (0x7 << ICM_CFG_OFF_IWAY)
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/* D-cache sets (# of cache lines) per way */
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#define DCM_CFG_OFF_DSET 0
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/* D-cache ways */
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#define DCM_CFG_OFF_DWAY 3
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#define DCM_CFG_MSK_DSET (0x7 << DCM_CFG_OFF_DSET)
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#define DCM_CFG_MSK_DWAY (0x7 << DCM_CFG_OFF_DWAY)
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/* I-cache line size */
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#define ICM_CFG_OFF_ISZ 6
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#define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ)
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/* D-cache line size */
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#define DCM_CFG_OFF_DSZ 6
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#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ)
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/*
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* The current upper bound for NDS32 L1 data cache line sizes is 32 bytes.
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* We use that value for aligning DMA buffers unless the board config has
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* specified an alternate cache line size.
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*/
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#ifdef CONFIG_SYS_CACHELINE_SIZE
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#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
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#else
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#define ARCH_DMA_MINALIGN 32
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#endif
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#endif /* _ASM_CACHE_H */
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