mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
7c6f274a36
This patch adds the necessary lowlevel init code, to enable SMP Linux booting. This code will be used with the platform specific Octeon Linux boot command "bootoctlinux", which starts a configurable number of cores into Linux. Additionally some erratas and lowlevel register initializations are copied from the original Cavium / Marvell U-Boot source code, enabling booting into the Linux kernel. Signed-off-by: Stefan Roese <sr@denx.de>
146 lines
3.1 KiB
ArmAsm
146 lines
3.1 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Stefan Roese <sr@denx.de>
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*/
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#include <config.h>
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#include <asm-offsets.h>
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#include <asm/cacheops.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include <mach/octeon-model.h>
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#define COP0_CVMCTL_REG $9,7 /* Cavium control */
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#define COP0_CVMMEMCTL_REG $11,7 /* Cavium memory control */
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#define COP0_PROC_ID_REG $15,0
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.set noreorder
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LEAF(lowlevel_init)
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/* Set LMEMSZ in CVMMEMCTL register */
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dmfc0 a0, COP0_CVMMEMCTL_REG
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dins a0, zero, 0, 9
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mfc0 a4, COP0_PROC_ID_REG
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li a5, OCTEON_CN63XX_PASS1_0 /* Octeon cn63xx pass1 chip id */
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bgt a5, a4, 2f
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ori a0, 0x104 /* setup 4 lines of scratch */
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ori a6, a5, 8 /* Octeon cn63xx pass2 chip id */
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bge a4, a6, 2f
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nop
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li a6, 4
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ins a0, a6, 11, 4 /* Set WBTHRESH=4 as per Core-14752 errata */
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2:
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dmtc0 a0, COP0_CVMMEMCTL_REG
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/* Set REPUN bit in CVMCTL register */
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dmfc0 a0, COP0_CVMCTL_REG
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ori a0, 1<<14 /* enable fixup of unaligned mem access */
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dmtc0 a0, COP0_CVMCTL_REG
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jr ra
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nop
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END(lowlevel_init)
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LEAF(mips_mach_early_init)
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move s0, ra
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bal __dummy
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nop
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__dummy:
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/* Get the actual address that we are running at */
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PTR_LA a7, __dummy
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dsubu t3, ra, a7 /* t3 now has reloc offset */
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PTR_LA t1, _start
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daddu t0, t1, t3 /* t0 now has actual address of _start */
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/* Calculate end address of copy loop */
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PTR_LA t2, _end
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daddiu t2, t2, 0x4000 /* Increase size to include appended DTB */
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daddiu t2, t2, 127
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ins t2, zero, 0, 7 /* Round up to cache line for memcpy */
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/* Copy ourself to the L2 cache from flash, 32 bytes at a time */
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1:
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ld a0, 0(t0)
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ld a1, 8(t0)
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ld a2, 16(t0)
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ld a3, 24(t0)
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sd a0, 0(t1)
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sd a1, 8(t1)
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sd a2, 16(t1)
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sd a3, 24(t1)
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addiu t0, 32
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addiu t1, 32
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bne t1, t2, 1b
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nop
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sync
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/*
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* Return to start.S now running from TEXT_BASE, which points
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* to DRAM address space, which effectively is L2 cache now.
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* This speeds up the init process extremely, especially the
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* DDR init code.
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*/
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dsubu s0, s0, t3 /* Fixup return address with reloc offset */
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jr.hb s0 /* Jump back with hazard barrier */
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nop
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END(mips_mach_early_init)
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LEAF(nmi_bootvector)
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/*
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* From Marvell original bootvector setup
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*/
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mfc0 k0, CP0_STATUS
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/* Enable 64-bit addressing, set ERL (should already be set) */
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ori k0, 0x84
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mtc0 k0, CP0_STATUS
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/* Core-14345, clear L1 Dcache virtual tags if the core hit an NMI */
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cache 17, 0($0)
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/*
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* Needed for Linux kernel booting, otherwise it hangs while
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* zero'ing all of CVMSEG
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*/
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dmfc0 a0, COP0_CVMMEMCTL_REG
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dins a0, zero, 0, 9
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ori a0, 0x104 /* setup 4 lines of scratch */
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dmtc0 a0, COP0_CVMMEMCTL_REG
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/*
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* Load parameters and entry point
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*/
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PTR_LA t9, nmi_handler_para
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sync
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ld s0, 0x00(t9)
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ld a0, 0x08(t9)
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ld a1, 0x10(t9)
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ld a2, 0x18(t9)
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ld a3, 0x20(t9)
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/* Finally jump to entry point (start kernel etc) */
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j s0
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nop
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END(nmi_bootvector)
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/*
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* Add here some space for the NMI parameters (entry point and args)
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*/
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.globl nmi_handler_para
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nmi_handler_para:
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.dword 0 // entry-point
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.dword 0 // arg0
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.dword 0 // arg1
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.dword 0 // arg2
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.dword 0 // arg3
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