mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
547 lines
21 KiB
C
547 lines
21 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* MCF5227x Internal Memory Map
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*/
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#ifndef __MCF5227X__
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#define __MCF5227X__
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/* Interrupt Controller (INTC) */
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#define INT0_LO_RSVD0 (0)
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#define INT0_LO_EPORT1 (1)
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#define INT0_LO_EPORT4 (4)
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#define INT0_LO_EPORT7 (7)
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#define INT0_LO_EDMA_00 (8)
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#define INT0_LO_EDMA_01 (9)
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#define INT0_LO_EDMA_02 (10)
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#define INT0_LO_EDMA_03 (11)
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#define INT0_LO_EDMA_04 (12)
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#define INT0_LO_EDMA_05 (13)
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#define INT0_LO_EDMA_06 (14)
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#define INT0_LO_EDMA_07 (15)
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#define INT0_LO_EDMA_08 (16)
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#define INT0_LO_EDMA_09 (17)
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#define INT0_LO_EDMA_10 (18)
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#define INT0_LO_EDMA_11 (19)
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#define INT0_LO_EDMA_12 (20)
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#define INT0_LO_EDMA_13 (21)
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#define INT0_LO_EDMA_14 (22)
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#define INT0_LO_EDMA_15 (23)
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#define INT0_LO_EDMA_ERR (24)
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#define INT0_LO_SCM_CWIC (25)
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#define INT0_LO_UART0 (26)
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#define INT0_LO_UART1 (27)
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#define INT0_LO_UART2 (28)
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#define INT0_LO_I2C (30)
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#define INT0_LO_DSPI (31)
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#define INT0_HI_DTMR0 (32)
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#define INT0_HI_DTMR1 (33)
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#define INT0_HI_DTMR2 (34)
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#define INT0_HI_DTMR3 (35)
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#define INT0_HI_SCMIR (62)
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#define INT0_HI_RTC_ISR (63)
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#define INT1_HI_CAN_BOFFINT (1)
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#define INT1_HI_CAN_ERRINT (3)
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#define INT1_HI_CAN_BUF0I (4)
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#define INT1_HI_CAN_BUF1I (5)
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#define INT1_HI_CAN_BUF2I (6)
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#define INT1_HI_CAN_BUF3I (7)
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#define INT1_HI_CAN_BUF4I (8)
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#define INT1_HI_CAN_BUF5I (9)
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#define INT1_HI_CAN_BUF6I (10)
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#define INT1_HI_CAN_BUF7I (11)
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#define INT1_HI_CAN_BUF8I (12)
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#define INT1_HI_CAN_BUF9I (13)
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#define INT1_HI_CAN_BUF10I (14)
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#define INT1_HI_CAN_BUF11I (15)
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#define INT1_HI_CAN_BUF12I (16)
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#define INT1_HI_CAN_BUF13I (17)
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#define INT1_HI_CAN_BUF14I (18)
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#define INT1_HI_CAN_BUF15I (19)
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#define INT1_HI_PIT0_PIF (43)
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#define INT1_HI_PIT1_PIF (44)
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#define INT1_HI_USBOTG_STS (47)
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#define INT1_HI_SSI_ISR (49)
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#define INT1_HI_PWM_INT (50)
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#define INT1_HI_LCDC_ISR (51)
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#define INT1_HI_CCM_UOCSR (53)
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#define INT1_HI_DSPI_EOQF (54)
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#define INT1_HI_DSPI_TFFF (55)
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#define INT1_HI_DSPI_TCF (56)
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#define INT1_HI_DSPI_TFUF (57)
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#define INT1_HI_DSPI_RFDF (58)
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#define INT1_HI_DSPI_RFOF (59)
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#define INT1_HI_DSPI_RFOF_TFUF (60)
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#define INT1_HI_TOUCH_ADC (61)
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#define INT1_HI_PLL_LOCKS (62)
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/*********************************************************************
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* Reset Controller Module (RCM)
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*********************************************************************/
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/* Bit definitions and macros for RCR */
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#define RCM_RCR_FRCRSTOUT (0x40)
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#define RCM_RCR_SOFTRST (0x80)
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/* Bit definitions and macros for RSR */
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#define RCM_RSR_LOL (0x01)
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#define RCM_RSR_WDR_CORE (0x02)
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#define RCM_RSR_EXT (0x04)
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#define RCM_RSR_POR (0x08)
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#define RCM_RSR_SOFT (0x20)
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/*********************************************************************
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* Chip Configuration Module (CCM)
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*********************************************************************/
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/* Bit definitions and macros for CCR */
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#define CCM_CCR_DRAMSEL (0x0100)
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#define CCM_CCR_CSC_UNMASK (0xFF3F)
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#define CCM_CCR_CSC_FBCS5_CS4 (0x00C0)
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#define CCM_CCR_CSC_FBCS5_A22 (0x0080)
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#define CCM_CCR_CSC_FB_A23_A22 (0x0040)
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#define CCM_CCR_LIMP (0x0020)
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#define CCM_CCR_LOAD (0x0010)
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#define CCM_CCR_BOOTPS_UNMASK (0xFFF3)
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#define CCM_CCR_BOOTPS_PS16 (0x0008)
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#define CCM_CCR_BOOTPS_PS8 (0x0004)
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#define CCM_CCR_BOOTPS_PS32 (0x0000)
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#define CCM_CCR_OSCMODE_OSCBYPASS (0x0002)
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/* Bit definitions and macros for RCON */
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#define CCM_RCON_CSC_UNMASK (0xFF3F)
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#define CCM_RCON_CSC_FBCS5_CS4 (0x00C0)
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#define CCM_RCON_CSC_FBCS5_A22 (0x0080)
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#define CCM_RCON_CSC_FB_A23_A22 (0x0040)
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#define CCM_RCON_LIMP (0x0020)
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#define CCM_RCON_LOAD (0x0010)
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#define CCM_RCON_BOOTPS_UNMASK (0xFFF3)
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#define CCM_RCON_BOOTPS_PS16 (0x0008)
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#define CCM_RCON_BOOTPS_PS8 (0x0004)
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#define CCM_RCON_BOOTPS_PS32 (0x0000)
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#define CCM_RCON_OSCMODE_OSCBYPASS (0x0002)
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/* Bit definitions and macros for CIR */
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#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6)
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#define CCM_CIR_PRN(x) ((x) & 0x003F)
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#define CCM_CIR_PIN_MCF52277 (0x0000)
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/* Bit definitions and macros for MISCCR */
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#define CCM_MISCCR_RTCSRC (0x4000)
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#define CCM_MISCCR_USBPUE (0x2000) /* USB transceiver pull-up */
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#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */
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#define CCM_MISCCR_BME (0x0800) /* Bus monitor ext en bit */
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#define CCM_MISCCR_BMT_65536 (0)
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#define CCM_MISCCR_BMT_32768 (1)
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#define CCM_MISCCR_BMT_16384 (2)
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#define CCM_MISCCR_BMT_8192 (3)
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#define CCM_MISCCR_BMT_4096 (4)
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#define CCM_MISCCR_BMT_2048 (5)
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#define CCM_MISCCR_BMT_1024 (6)
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#define CCM_MISCCR_BMT_512 (7)
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#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */
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#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */
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#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */
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#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
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#define CCM_MISCCR_LCDCHEN (0x0004) /* LCD Int CLK en */
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#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense pol */
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#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
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/* Bit definitions and macros for CDR */
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#define CCM_CDR_USBDIV(x) (((x)&0x0003)<<12)
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#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clk div */
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#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clk div */
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/* Bit definitions and macros for UOCSR */
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#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (rd-only) */
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#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (rd-only) */
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#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (rd-only) */
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#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor en (rd-only) */
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#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (rd-only) */
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#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */
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#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */
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#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */
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#define CCM_UOCSR_SEND (0x0010) /* Session end */
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#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */
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#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt en */
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#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down en */
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/*********************************************************************
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* General Purpose I/O Module (GPIO)
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*********************************************************************/
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/* Bit definitions and macros for PAR_BE */
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#define GPIO_PAR_BE_UNMASK (0x0F)
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#define GPIO_PAR_BE_BE3_BE3 (0x08)
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#define GPIO_PAR_BE_BE3_GPIO (0x00)
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#define GPIO_PAR_BE_BE2_BE2 (0x04)
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#define GPIO_PAR_BE_BE2_GPIO (0x00)
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#define GPIO_PAR_BE_BE1_BE1 (0x02)
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#define GPIO_PAR_BE_BE1_GPIO (0x00)
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#define GPIO_PAR_BE_BE0_BE0 (0x01)
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#define GPIO_PAR_BE_BE0_GPIO (0x00)
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/* Bit definitions and macros for PAR_CS */
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#define GPIO_PAR_CS_CS3 (0x10)
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#define GPIO_PAR_CS_CS2 (0x08)
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#define GPIO_PAR_CS_CS1_FBCS1 (0x06)
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#define GPIO_PAR_CS_CS1_SDCS1 (0x04)
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#define GPIO_PAR_CS_CS1_GPIO (0x00)
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#define GPIO_PAR_CS_CS0 (0x01)
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/* Bit definitions and macros for PAR_FBCTL */
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#define GPIO_PAR_FBCTL_OE (0x80)
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#define GPIO_PAR_FBCTL_TA (0x40)
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#define GPIO_PAR_FBCTL_RW (0x20)
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#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7)
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#define GPIO_PAR_FBCTL_TS_FBTS (0x18)
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#define GPIO_PAR_FBCTL_TS_DMAACK (0x10)
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#define GPIO_PAR_FBCTL_TS_GPIO (0x00)
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/* Bit definitions and macros for PAR_FECI2C */
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#define GPIO_PAR_I2C_SCL_UNMASK (0xF3)
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#define GPIO_PAR_I2C_SCL_SCL (0x0C)
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#define GPIO_PAR_I2C_SCL_CANTXD (0x08)
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#define GPIO_PAR_I2C_SCL_U2TXD (0x04)
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#define GPIO_PAR_I2C_SCL_GPIO (0x00)
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#define GPIO_PAR_I2C_SDA_UNMASK (0xFC)
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#define GPIO_PAR_I2C_SDA_SDA (0x03)
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#define GPIO_PAR_I2C_SDA_CANRXD (0x02)
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#define GPIO_PAR_I2C_SDA_U2RXD (0x01)
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#define GPIO_PAR_I2C_SDA_GPIO (0x00)
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/* Bit definitions and macros for PAR_UART */
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#define GPIO_PAR_UART_U1CTS_UNMASK (0x3FFF)
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#define GPIO_PAR_UART_U1CTS_U1CTS (0xC000)
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#define GPIO_PAR_UART_U1CTS_SSIBCLK (0x8000)
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#define GPIO_PAR_UART_U1CTS_LCDCLS (0x4000)
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#define GPIO_PAR_UART_U1CTS_GPIO (0x0000)
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#define GPIO_PAR_UART_U1RTS_UNMASK (0xCFFF)
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#define GPIO_PAR_UART_U1RTS_U1RTS (0x3000)
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#define GPIO_PAR_UART_U1RTS_SSIFS (0x2000)
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#define GPIO_PAR_UART_U1RTS_LCDPS (0x1000)
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#define GPIO_PAR_UART_U1RTS_GPIO (0x0000)
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#define GPIO_PAR_UART_U1RXD_UNMASK (0xF3FF)
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#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00)
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#define GPIO_PAR_UART_U1RXD_SSIRXD (0x0800)
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#define GPIO_PAR_UART_U1RXD_GPIO (0x0000)
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#define GPIO_PAR_UART_U1TXD_UNMASK (0xFCFF)
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#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300)
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#define GPIO_PAR_UART_U1TXD_SSITXD (0x0200)
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#define GPIO_PAR_UART_U1TXD_GPIO (0x0000)
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#define GPIO_PAR_UART_U0CTS_UNMASK (0xFF3F)
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#define GPIO_PAR_UART_U0CTS_U0CTS (0x00C0)
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#define GPIO_PAR_UART_U0CTS_T1OUT (0x0080)
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#define GPIO_PAR_UART_U0CTS_USBVBUSEN (0x0040)
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#define GPIO_PAR_UART_U0CTS_GPIO (0x0000)
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#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFCF)
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#define GPIO_PAR_UART_U0RTS_U0RTS (0x0030)
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#define GPIO_PAR_UART_U0RTS_T1IN (0x0020)
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#define GPIO_PAR_UART_U0RTS_USBVBUSOC (0x0010)
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#define GPIO_PAR_UART_U0RTS_GPIO (0x0000)
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#define GPIO_PAR_UART_U0RXD_UNMASK (0xFFF3)
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#define GPIO_PAR_UART_U0RXD_U0RXD (0x000C)
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#define GPIO_PAR_UART_U0RXD_CANRX (0x0008)
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#define GPIO_PAR_UART_U0RXD_GPIO (0x0000)
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#define GPIO_PAR_UART_U0TXD_UNMASK (0xFFFC)
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#define GPIO_PAR_UART_U0TXD_U0TXD (0x0003)
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#define GPIO_PAR_UART_U0TXD_CANTX (0x0002)
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#define GPIO_PAR_UART_U0TXD_GPIO (0x0000)
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/* Bit definitions and macros for PAR_DSPI */
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#define GPIO_PAR_DSPI_PCS0_UNMASK (0x3F)
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#define GPIO_PAR_DSPI_PCS0_PCS0 (0xC0)
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#define GPIO_PAR_DSPI_PCS0_U2RTS (0x80)
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#define GPIO_PAR_DSPI_PCS0_GPIO (0x00)
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#define GPIO_PAR_DSPI_SIN_UNMASK (0xCF)
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#define GPIO_PAR_DSPI_SIN_SIN (0x30)
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#define GPIO_PAR_DSPI_SIN_U2RXD (0x20)
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#define GPIO_PAR_DSPI_SIN_GPIO (0x00)
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#define GPIO_PAR_DSPI_SOUT_UNMASK (0xF3)
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#define GPIO_PAR_DSPI_SOUT_SOUT (0x0C)
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#define GPIO_PAR_DSPI_SOUT_U2TXD (0x08)
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#define GPIO_PAR_DSPI_SOUT_GPIO (0x00)
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#define GPIO_PAR_DSPI_SCK_UNMASK (0xFC)
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#define GPIO_PAR_DSPI_SCK_SCK (0x03)
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#define GPIO_PAR_DSPI_SCK_U2CTS (0x02)
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#define GPIO_PAR_DSPI_SCK_GPIO (0x00)
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/* Bit definitions and macros for PAR_TIMER */
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#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F)
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#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
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#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
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#define GPIO_PAR_TIMER_T3IN_SSIMCLK (0x40)
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#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
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#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF)
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#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
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#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
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#define GPIO_PAR_TIMER_T2IN_DSPIPCS2 (0x10)
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#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
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#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3)
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#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
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#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
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#define GPIO_PAR_TIMER_T1IN_LCDCONTRAST (0x04)
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#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
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#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC)
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#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
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#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
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#define GPIO_PAR_TIMER_T0IN_LCDREV (0x01)
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#define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
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/* Bit definitions and macros for GPIO_PAR_LCDCTL */
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#define GPIO_PAR_LCDCTL_ACDOE_UNMASK (0xE7)
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#define GPIO_PAR_LCDCTL_ACDOE_ACDOE (0x18)
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#define GPIO_PAR_LCDCTL_ACDOE_SPLSPR (0x10)
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#define GPIO_PAR_LCDCTL_ACDOE_GPIO (0x00)
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#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x04)
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#define GPIO_PAR_LCDCTL_LP_HSYNC (0x02)
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#define GPIO_PAR_LCDCTL_LSCLK (0x01)
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/* Bit definitions and macros for PAR_IRQ */
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#define GPIO_PAR_IRQ_IRQ4_UNMASK (0xF3)
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#define GPIO_PAR_IRQ_IRQ4_SSIINPCLK (0x0C)
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#define GPIO_PAR_IRQ_IRQ4_DMAREQ0 (0x08)
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#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
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#define GPIO_PAR_IRQ_IRQ1_UNMASK (0xFC)
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#define GPIO_PAR_IRQ_IRQ1_PCIINT (0x03)
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#define GPIO_PAR_IRQ_IRQ1_USBCLKIN (0x02)
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#define GPIO_PAR_IRQ_IRQ1_SSICLKIN (0x01)
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#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
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/* Bit definitions and macros for GPIO_PAR_LCDH */
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#define GPIO_PAR_LCDH_LD17_UNMASK (0xFFFFF3FF)
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#define GPIO_PAR_LCDH_LD17_LD17 (0x00000C00)
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#define GPIO_PAR_LCDH_LD17_LD11 (0x00000800)
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#define GPIO_PAR_LCDH_LD17_GPIO (0x00000000)
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#define GPIO_PAR_LCDH_LD16_UNMASK (0xFFFFFCFF)
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#define GPIO_PAR_LCDH_LD16_LD16 (0x00000300)
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#define GPIO_PAR_LCDH_LD16_LD10 (0x00000200)
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#define GPIO_PAR_LCDH_LD16_GPIO (0x00000000)
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#define GPIO_PAR_LCDH_LD15_UNMASK (0xFFFFFF3F)
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#define GPIO_PAR_LCDH_LD15_LD15 (0x000000C0)
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#define GPIO_PAR_LCDH_LD15_LD9 (0x00000080)
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#define GPIO_PAR_LCDH_LD15_GPIO (0x00000000)
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#define GPIO_PAR_LCDH_LD14_UNMASK (0xFFFFFFCF)
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#define GPIO_PAR_LCDH_LD14_LD14 (0x00000030)
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#define GPIO_PAR_LCDH_LD14_LD8 (0x00000020)
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#define GPIO_PAR_LCDH_LD14_GPIO (0x00000000)
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#define GPIO_PAR_LCDH_LD13_UNMASK (0xFFFFFFF3)
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#define GPIO_PAR_LCDH_LD13_LD13 (0x0000000C)
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#define GPIO_PAR_LCDH_LD13_CANTX (0x00000008)
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#define GPIO_PAR_LCDH_LD13_GPIO (0x00000000)
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#define GPIO_PAR_LCDH_LD12_UNMASK (0xFFFFFFFC)
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#define GPIO_PAR_LCDH_LD12_LD12 (0x00000003)
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#define GPIO_PAR_LCDH_LD12_CANRX (0x00000002)
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#define GPIO_PAR_LCDH_LD12_GPIO (0x00000000)
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/* Bit definitions and macros for GPIO_PAR_LCDL */
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#define GPIO_PAR_LCDL_LD11_UNMASK (0x3FFFFFFF)
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#define GPIO_PAR_LCDL_LD11_LD11 (0xC0000000)
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#define GPIO_PAR_LCDL_LD11_LD7 (0x80000000)
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#define GPIO_PAR_LCDL_LD11_GPIO (0x00000000)
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#define GPIO_PAR_LCDL_LD10_UNMASK (0xCFFFFFFF)
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#define GPIO_PAR_LCDL_LD10_LD10 (0x30000000)
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#define GPIO_PAR_LCDL_LD10_LD6 (0x20000000)
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#define GPIO_PAR_LCDL_LD10_GPIO (0x00000000)
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#define GPIO_PAR_LCDL_LD9_UNMASK (0xF3FFFFFF)
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#define GPIO_PAR_LCDL_LD9_LD9 (0x0C000000)
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#define GPIO_PAR_LCDL_LD9_LD5 (0x08000000)
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#define GPIO_PAR_LCDL_LD9_GPIO (0x00000000)
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#define GPIO_PAR_LCDL_LD8_UNMASK (0xFCFFFFFF)
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#define GPIO_PAR_LCDL_LD8_LD8 (0x03000000)
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#define GPIO_PAR_LCDL_LD8_LD4 (0x02000000)
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#define GPIO_PAR_LCDL_LD8_GPIO (0x00000000)
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#define GPIO_PAR_LCDL_LD7_UNMASK (0xFF3FFFFF)
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#define GPIO_PAR_LCDL_LD7_LD7 (0x00C00000)
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#define GPIO_PAR_LCDL_LD7_PWM7 (0x00800000)
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#define GPIO_PAR_LCDL_LD7_GPIO (0x00000000)
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#define GPIO_PAR_LCDL_LD6_UNMASK (0xFFCFFFFF)
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#define GPIO_PAR_LCDL_LD6_LD6 (0x00300000)
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#define GPIO_PAR_LCDL_LD6_PWM5 (0x00200000)
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#define GPIO_PAR_LCDL_LD6_GPIO (0x00000000)
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#define GPIO_PAR_LCDL_LD5_UNMASK (0xFFF3FFFF)
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#define GPIO_PAR_LCDL_LD5_LD5 (0x000C0000)
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#define GPIO_PAR_LCDL_LD5_LD3 (0x00080000)
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#define GPIO_PAR_LCDL_LD5_GPIO (0x00000000)
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#define GPIO_PAR_LCDL_LD4_UNMASK (0xFFFCFFFF)
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#define GPIO_PAR_LCDL_LD4_LD4 (0x00030000)
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#define GPIO_PAR_LCDL_LD4_LD2 (0x00020000)
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#define GPIO_PAR_LCDL_LD4_GPIO (0x00000000)
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#define GPIO_PAR_LCDL_LD3_UNMASK (0xFFFF3FFF)
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#define GPIO_PAR_LCDL_LD3_LD3 (0x0000C000)
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#define GPIO_PAR_LCDL_LD3_LD1 (0x00008000)
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#define GPIO_PAR_LCDL_LD3_GPIO (0x00000000)
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#define GPIO_PAR_LCDL_LD2_UNMASK (0xFFFFCFFF)
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#define GPIO_PAR_LCDL_LD2_LD2 (0x00003000)
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#define GPIO_PAR_LCDL_LD2_LD0 (0x00002000)
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#define GPIO_PAR_LCDL_LD2_GPIO (0x00000000)
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#define GPIO_PAR_LCDL_LD1_UNMASK (0xFFFFF3FF)
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#define GPIO_PAR_LCDL_LD1_LD1 (0x00000C00)
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#define GPIO_PAR_LCDL_LD1_PWM3 (0x00000800)
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#define GPIO_PAR_LCDL_LD1_GPIO (0x00000000)
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#define GPIO_PAR_LCDL_LD0_UNMASK (0xFFFFFCFF)
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#define GPIO_PAR_LCDL_LD0_LD0 (0x00000300)
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#define GPIO_PAR_LCDL_LD0_PWM1 (0x00000200)
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#define GPIO_PAR_LCDL_LD0_GPIO (0x00000000)
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/* Bit definitions and macros for MSCR_FB */
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#define GPIO_MSCR_FB_DUPPER_UNMASK (0xCF)
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#define GPIO_MSCR_FB_DUPPER_25V_33V (0x30)
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#define GPIO_MSCR_FB_DUPPER_FULL_18V (0x20)
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#define GPIO_MSCR_FB_DUPPER_OD (0x10)
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#define GPIO_MSCR_FB_DUPPER_HALF_18V (0x00)
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#define GPIO_MSCR_FB_DLOWER_UNMASK (0xF3)
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#define GPIO_MSCR_FB_DLOWER_25V_33V (0x0C)
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#define GPIO_MSCR_FB_DLOWER_FULL_18V (0x08)
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#define GPIO_MSCR_FB_DLOWER_OD (0x04)
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#define GPIO_MSCR_FB_DLOWER_HALF_18V (0x00)
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#define GPIO_MSCR_FB_ADDRCTL_UNMASK (0xFC)
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#define GPIO_MSCR_FB_ADDRCTL_25V_33V (0x03)
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#define GPIO_MSCR_FB_ADDRCTL_FULL_18V (0x02)
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#define GPIO_MSCR_FB_ADDRCTL_OD (0x01)
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#define GPIO_MSCR_FB_ADDRCTL_HALF_18V (0x00)
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/* Bit definitions and macros for MSCR_SDRAM */
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#define GPIO_MSCR_SDRAM_SDCLKB_UNMASK (0xCF)
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#define GPIO_MSCR_SDRAM_SDCLKB_25V_33V (0x30)
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#define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V (0x20)
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#define GPIO_MSCR_SDRAM_SDCLKB_OD (0x10)
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#define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V (0x00)
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#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3)
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#define GPIO_MSCR_SDRAM_SDCLK_25V_33V (0x0C)
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#define GPIO_MSCR_SDRAM_SDCLK_FULL_18V (0x08)
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#define GPIO_MSCR_SDRAM_SDCLK_OPD (0x04)
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#define GPIO_MSCR_SDRAM_SDCLK_HALF_18V (0x00)
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#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC)
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#define GPIO_MSCR_SDRAM_SDCTL_25V_33V (0x03)
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#define GPIO_MSCR_SDRAM_SDCTL_FULL_18V (0x02)
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#define GPIO_MSCR_SDRAM_SDCTL_OPD (0x01)
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#define GPIO_MSCR_SDRAM_SDCTL_HALF_18V (0x00)
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/* Bit definitions and macros for Drive Strength Control */
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#define DSCR_LOAD_50PF (0x03)
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#define DSCR_LOAD_30PF (0x02)
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#define DSCR_LOAD_20PF (0x01)
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#define DSCR_LOAD_10PF (0x00)
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/*********************************************************************
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* SDRAM Controller (SDRAMC)
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*********************************************************************/
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/* Bit definitions and macros for SDMR */
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#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
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#define SDRAMC_SDMR_CMD (0x00010000) /* Command */
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#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
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#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
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#define SDRAMC_SDMR_BK_LMR (0x00000000)
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#define SDRAMC_SDMR_BK_LEMR (0x40000000)
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/* Bit definitions and macros for SDCR */
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#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
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#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
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#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
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#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
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#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
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#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */
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#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
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#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */
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#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
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#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
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#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
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#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */
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#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */
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#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000)
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/* Bit definitions and macros for SDCFG1 */
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#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */
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#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */
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#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */
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#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */
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#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */
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#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */
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#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */
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/* Bit definitions and macros for SDCFG2 */
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#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */
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#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */
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#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */
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#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */
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/* Bit definitions and macros for SDCS group */
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#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
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#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
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#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
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#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
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#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
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#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
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#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
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#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
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#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
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#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
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#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
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#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
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#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
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#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
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#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
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#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
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#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
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/*********************************************************************
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* Phase Locked Loop (PLL)
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*********************************************************************/
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/* Bit definitions and macros for PCR */
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#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */
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#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for bus/flexbus clock frequency */
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#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for SDRAM clock frequency */
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#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */
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#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */
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#define PLL_PCR_PFDR_MASK (0x000F0000)
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#define PLL_PCR_OUTDIV5_MASK (0x000F0000)
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#define PLL_PCR_OUTDIV3_MASK (0x00000F00)
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#define PLL_PCR_OUTDIV2_MASK (0x000000F0)
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#define PLL_PCR_OUTDIV1_MASK (0x0000000F)
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/* Bit definitions and macros for PSR */
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#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */
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#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */
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#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */
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#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */
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/********************************************************************/
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#endif /* __MCF5227X__ */
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