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https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
259 lines
7.1 KiB
C
259 lines
7.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* MCF547x_8x Internal Memory Map
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*/
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#ifndef __IMMAP_547x_8x__
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#define __IMMAP_547x_8x__
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#define MMAP_SIU (CONFIG_SYS_MBAR + 0x00000000)
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#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000100)
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#define MMAP_XARB (CONFIG_SYS_MBAR + 0x00000240)
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#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000500)
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#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000700)
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#define MMAP_GPTMR (CONFIG_SYS_MBAR + 0x00000800)
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#define MMAP_SLT0 (CONFIG_SYS_MBAR + 0x00000900)
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#define MMAP_SLT1 (CONFIG_SYS_MBAR + 0x00000910)
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#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000A00)
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#define MMAP_PCI (CONFIG_SYS_MBAR + 0x00000B00)
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#define MMAP_PCIARB (CONFIG_SYS_MBAR + 0x00000C00)
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#define MMAP_EXTDMA (CONFIG_SYS_MBAR + 0x00000D00)
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#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00000F00)
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#define MMAP_CTM (CONFIG_SYS_MBAR + 0x00007F00)
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#define MMAP_MCDMA (CONFIG_SYS_MBAR + 0x00008000)
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#define MMAP_SCPCI (CONFIG_SYS_MBAR + 0x00008400)
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#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00008600)
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#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00008700)
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#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00008800)
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#define MMAP_UART3 (CONFIG_SYS_MBAR + 0x00008900)
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#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x00008A00)
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#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00008F00)
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#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00009000)
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#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00009800)
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#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x0000A000)
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#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x0000A800)
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#define MMAP_USBD (CONFIG_SYS_MBAR + 0x0000B000)
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#define MMAP_SRAM (CONFIG_SYS_MBAR + 0x00010000)
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#define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001FF00)
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#define MMAP_SEC (CONFIG_SYS_MBAR + 0x00020000)
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#include <asm/coldfire/dspi.h>
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#include <asm/coldfire/eport.h>
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#include <asm/coldfire/flexbus.h>
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#include <asm/coldfire/flexcan.h>
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#include <asm/coldfire/intctrl.h>
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typedef struct siu {
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u32 mbar; /* 0x00 */
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u32 drv; /* 0x04 */
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u32 rsvd1[2]; /* 0x08 - 0x1F */
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u32 sbcr; /* 0x10 */
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u32 rsvd2[3]; /* 0x14 - 0x1F */
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u32 cs0cfg; /* 0x20 */
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u32 cs1cfg; /* 0x24 */
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u32 cs2cfg; /* 0x28 */
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u32 cs3cfg; /* 0x2C */
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u32 rsvd3[2]; /* 0x30 - 0x37 */
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u32 secsacr; /* 0x38 */
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u32 rsvd4[2]; /* 0x3C - 0x43 */
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u32 rsr; /* 0x44 */
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u32 rsvd5[2]; /* 0x48 - 0x4F */
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u32 jtagid; /* 0x50 */
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} siu_t;
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typedef struct sdram {
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u32 mode; /* 0x00 */
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u32 ctrl; /* 0x04 */
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u32 cfg1; /* 0x08 */
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u32 cfg2; /* 0x0c */
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} sdram_t;
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typedef struct xlb_arb {
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u32 cfg; /* 0x240 */
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u32 ver; /* 0x244 */
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u32 sr; /* 0x248 */
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u32 imr; /* 0x24c */
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u32 adrcap; /* 0x250 */
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u32 sigcap; /* 0x254 */
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u32 adrto; /* 0x258 */
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u32 datto; /* 0x25c */
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u32 busto; /* 0x260 */
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u32 prien; /* 0x264 */
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u32 pri; /* 0x268 */
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} xlbarb_t;
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typedef struct gptmr {
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u8 ocpw;
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u8 octict;
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u8 ctrl;
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u8 mode;
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u16 pre; /* Prescale */
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u16 cnt;
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u16 pwmwidth;
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u8 pwmop; /* Output Polarity */
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u8 pwmld; /* Immediate Update */
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u16 cap; /* Capture internal counter */
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u8 ovfpin; /* Ovf and Pin */
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u8 intr; /* Interrupts */
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} gptmr_t;
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typedef struct canex_ctrl {
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can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
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} canex_t;
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typedef struct slt {
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u32 tcnt; /* 0x00 */
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u32 cr; /* 0x04 */
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u32 cnt; /* 0x08 */
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u32 sr; /* 0x0C */
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} slt_t;
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typedef struct gpio {
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/* Port Output Data Registers */
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u8 podr_fbctl; /*0x00 */
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u8 podr_fbcs; /*0x01 */
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u8 podr_dma; /*0x02 */
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u8 rsvd1; /*0x03 */
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u8 podr_fec0h; /*0x04 */
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u8 podr_fec0l; /*0x05 */
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u8 podr_fec1h; /*0x06 */
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u8 podr_fec1l; /*0x07 */
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u8 podr_feci2c; /*0x08 */
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u8 podr_pcibg; /*0x09 */
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u8 podr_pcibr; /*0x0A */
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u8 rsvd2; /*0x0B */
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u8 podr_psc3psc2; /*0x0C */
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u8 podr_psc1psc0; /*0x0D */
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u8 podr_dspi; /*0x0E */
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u8 rsvd3; /*0x0F */
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/* Port Data Direction Registers */
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u8 pddr_fbctl; /*0x10 */
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u8 pddr_fbcs; /*0x11 */
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u8 pddr_dma; /*0x12 */
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u8 rsvd4; /*0x13 */
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u8 pddr_fec0h; /*0x14 */
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u8 pddr_fec0l; /*0x15 */
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u8 pddr_fec1h; /*0x16 */
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u8 pddr_fec1l; /*0x17 */
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u8 pddr_feci2c; /*0x18 */
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u8 pddr_pcibg; /*0x19 */
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u8 pddr_pcibr; /*0x1A */
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u8 rsvd5; /*0x1B */
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u8 pddr_psc3psc2; /*0x1C */
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u8 pddr_psc1psc0; /*0x1D */
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u8 pddr_dspi; /*0x1E */
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u8 rsvd6; /*0x1F */
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/* Port Pin Data/Set Data Registers */
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u8 ppdsdr_fbctl; /*0x20 */
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u8 ppdsdr_fbcs; /*0x21 */
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u8 ppdsdr_dma; /*0x22 */
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u8 rsvd7; /*0x23 */
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u8 ppdsdr_fec0h; /*0x24 */
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u8 ppdsdr_fec0l; /*0x25 */
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u8 ppdsdr_fec1h; /*0x26 */
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u8 ppdsdr_fec1l; /*0x27 */
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u8 ppdsdr_feci2c; /*0x28 */
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u8 ppdsdr_pcibg; /*0x29 */
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u8 ppdsdr_pcibr; /*0x2A */
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u8 rsvd8; /*0x2B */
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u8 ppdsdr_psc3psc2; /*0x2C */
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u8 ppdsdr_psc1psc0; /*0x2D */
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u8 ppdsdr_dspi; /*0x2E */
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u8 rsvd9; /*0x2F */
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/* Port Clear Output Data Registers */
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u8 pclrr_fbctl; /*0x30 */
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u8 pclrr_fbcs; /*0x31 */
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u8 pclrr_dma; /*0x32 */
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u8 rsvd10; /*0x33 */
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u8 pclrr_fec0h; /*0x34 */
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u8 pclrr_fec0l; /*0x35 */
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u8 pclrr_fec1h; /*0x36 */
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u8 pclrr_fec1l; /*0x37 */
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u8 pclrr_feci2c; /*0x38 */
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u8 pclrr_pcibg; /*0x39 */
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u8 pclrr_pcibr; /*0x3A */
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u8 rsvd11; /*0x3B */
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u8 pclrr_psc3psc2; /*0x3C */
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u8 pclrr_psc1psc0; /*0x3D */
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u8 pclrr_dspi; /*0x3E */
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u8 rsvd12; /*0x3F */
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/* Pin Assignment Registers */
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u16 par_fbctl; /*0x40 */
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u8 par_fbcs; /*0x42 */
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u8 par_dma; /*0x43 */
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u16 par_feci2cirq; /*0x44 */
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u16 rsvd13; /*0x46 */
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u16 par_pcibg; /*0x48 */
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u16 par_pcibr; /*0x4A */
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u8 par_psc3; /*0x4C */
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u8 par_psc2; /*0x4D */
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u8 par_psc1; /*0x4E */
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u8 par_psc0; /*0x4F */
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u16 par_dspi; /*0x50 */
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u8 par_timer; /*0x52 */
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u8 rsvd14; /*0x53 */
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} gpio_t;
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typedef struct pci {
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u32 idr; /* 0x00 Device Id / Vendor Id */
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u32 scr; /* 0x04 Status / command */
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u32 ccrir; /* 0x08 Class Code / Revision Id */
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u32 cr1; /* 0x0c Configuration 1 */
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u32 bar0; /* 0x10 Base address register 0 */
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u32 bar1; /* 0x14 Base address register 1 */
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u32 bar2; /* 0x18 NA */
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u32 bar3; /* 0x1c NA */
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u32 bar4; /* 0x20 NA */
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u32 bar5; /* 0x24 NA */
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u32 ccpr; /* 0x28 Cardbus CIS Pointer */
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u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID */
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u32 erbar; /* 0x30 Expansion ROM Base Address */
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u32 cpr; /* 0x34 Capabilities Pointer */
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u32 rsvd1; /* 0x38 */
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u32 cr2; /* 0x3c Configuration 2 */
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u32 rsvd2[8]; /* 0x40 - 0x5f */
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/* General control / status registers */
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u32 gscr; /* 0x60 Global Status / Control */
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u32 tbatr0a; /* 0x64 Target Base Adr Translation 0 */
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u32 tbatr1a; /* 0x68 Target Base Adr Translation 1 */
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u32 tcr1; /* 0x6c Target Control 1 Register */
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u32 iw0btar; /* 0x70 Initiator Win 0 Base/Translation adr */
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u32 iw1btar; /* 0x74 Initiator Win 1 Base/Translation adr */
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u32 iw2btar; /* 0x78 NA */
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u32 rsvd3; /* 0x7c */
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u32 iwcr; /* 0x80 Initiator Window Configuration */
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u32 icr; /* 0x84 Initiator Control */
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u32 isr; /* 0x88 Initiator Status */
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u32 tcr2; /* 0x8c NA */
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u32 tbatr0; /* 0x90 NA */
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u32 tbatr1; /* 0x94 NA */
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u32 tbatr2; /* 0x98 NA */
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u32 tbatr3; /* 0x9c NA */
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u32 tbatr4; /* 0xa0 NA */
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u32 tbatr5; /* 0xa4 NA */
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u32 intr; /* 0xa8 NA */
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u32 rsvd4[19]; /* 0xac - 0xf7 */
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u32 car; /* 0xf8 Configuration Address */
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} pci_t;
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typedef struct pci_arbiter {
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/* Pci Arbiter Registers */
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union {
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u32 acr; /* Arbiter Control */
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u32 asr; /* Arbiter Status */
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};
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} pciarb_t;
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#endif /* __IMMAP_547x_8x__ */
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