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04e5dd5115
Add basic ethernet controller devicetree nodes for all ColdFire families. Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
73 lines
1.4 KiB
Plaintext
73 lines
1.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
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*/
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/ {
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compatible = "fsl,mcf54x5";
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aliases {
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/* TO DO, clarify on serial, this SoC seems to have SPC and
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* no UARTS.
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*/
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spi0 = &dspi0;
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fec0 = &fec0;
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fec1 = &fec1;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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mbar: mbar@80000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x80000000 0x10000>;
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reg = <0x80000000 0x10000>;
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dspi0: dspi@8a00 {
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compatible = "fsl,mcf-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x8a00 0x100>;
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spi-max-frequency = <50000000>;
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num-cs = <4>;
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spi-mode = <0>;
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status = "disabled";
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};
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fec0: ethernet@9000 {
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compatible = "fsl,mcf-dma-fec";
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reg = <0x9000 0x800>;
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mii-base = <0>;
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max-speed = <100>;
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timeout-loop = <50000>;
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rx-task = <0>;
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tx-task = <1>;
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rx-piority = <6>;
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tx-piority = <7>;
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rx-init = <16>;
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tx-init = <17>;
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status = "disabled";
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};
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fec1: ethernet@9800 {
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compatible = "fsl,mcf-dma-fec";
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reg = <0x9800 0x800>;
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mii-base = <1>;
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max-speed = <100>;
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timeout-loop = <50000>;
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rx-task = <2>;
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tx-task = <3>;
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rx-piority = <6>;
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tx-piority = <7>;
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rx-init = <30>;
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tx-init = <31>;
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status = "disabled";
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};
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};
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};
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};
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