305 lines
6.4 KiB
C
305 lines
6.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012-2015 Panasonic Corporation
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* Copyright (C) 2015-2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <init.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/printk.h>
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#include <linux/sizes.h>
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#include <asm/global_data.h>
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#include <asm/u-boot.h>
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#include "init.h"
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#include "sg-regs.h"
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#include "soc-info.h"
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DECLARE_GLOBAL_DATA_PTR;
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struct uniphier_dram_map {
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unsigned long base;
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unsigned long size;
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};
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static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map,
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unsigned long sparse_ch1_base, bool have_ch2)
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{
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unsigned long size;
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u32 val;
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val = readl(sg_base + SG_MEMCONF);
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/* set up ch0 */
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dram_map[0].base = 0x80000000;
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switch (val & SG_MEMCONF_CH0_SZ_MASK) {
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case SG_MEMCONF_CH0_SZ_64M:
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size = SZ_64M;
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break;
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case SG_MEMCONF_CH0_SZ_128M:
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size = SZ_128M;
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break;
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case SG_MEMCONF_CH0_SZ_256M:
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size = SZ_256M;
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break;
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case SG_MEMCONF_CH0_SZ_512M:
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size = SZ_512M;
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break;
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case SG_MEMCONF_CH0_SZ_1G:
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size = SZ_1G;
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break;
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default:
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pr_err("error: invalid value is set to MEMCONF ch0 size\n");
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return -EINVAL;
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}
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if ((val & SG_MEMCONF_CH0_NUM_MASK) == SG_MEMCONF_CH0_NUM_2)
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size *= 2;
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dram_map[0].size = size;
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/* set up ch1 */
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dram_map[1].base = dram_map[0].base + size;
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if (val & SG_MEMCONF_SPARSEMEM) {
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if (dram_map[1].base > sparse_ch1_base) {
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pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n");
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pr_warn("Only ch0 is available\n");
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dram_map[1].base = 0;
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return 0;
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}
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dram_map[1].base = sparse_ch1_base;
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}
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switch (val & SG_MEMCONF_CH1_SZ_MASK) {
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case SG_MEMCONF_CH1_SZ_64M:
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size = SZ_64M;
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break;
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case SG_MEMCONF_CH1_SZ_128M:
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size = SZ_128M;
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break;
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case SG_MEMCONF_CH1_SZ_256M:
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size = SZ_256M;
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break;
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case SG_MEMCONF_CH1_SZ_512M:
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size = SZ_512M;
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break;
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case SG_MEMCONF_CH1_SZ_1G:
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size = SZ_1G;
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break;
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default:
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pr_err("error: invalid value is set to MEMCONF ch1 size\n");
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return -EINVAL;
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}
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if ((val & SG_MEMCONF_CH1_NUM_MASK) == SG_MEMCONF_CH1_NUM_2)
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size *= 2;
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dram_map[1].size = size;
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if (!have_ch2 || val & SG_MEMCONF_CH2_DISABLE)
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return 0;
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/* set up ch2 */
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dram_map[2].base = dram_map[1].base + size;
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switch (val & SG_MEMCONF_CH2_SZ_MASK) {
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case SG_MEMCONF_CH2_SZ_64M:
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size = SZ_64M;
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break;
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case SG_MEMCONF_CH2_SZ_128M:
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size = SZ_128M;
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break;
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case SG_MEMCONF_CH2_SZ_256M:
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size = SZ_256M;
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break;
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case SG_MEMCONF_CH2_SZ_512M:
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size = SZ_512M;
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break;
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case SG_MEMCONF_CH2_SZ_1G:
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size = SZ_1G;
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break;
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default:
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pr_err("error: invalid value is set to MEMCONF ch2 size\n");
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return -EINVAL;
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}
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if ((val & SG_MEMCONF_CH2_NUM_MASK) == SG_MEMCONF_CH2_NUM_2)
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size *= 2;
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dram_map[2].size = size;
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return 0;
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}
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static int uniphier_ld4_dram_map_get(struct uniphier_dram_map dram_map[])
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{
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return uniphier_memconf_decode(dram_map, 0xc0000000, false);
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}
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static int uniphier_pro4_dram_map_get(struct uniphier_dram_map dram_map[])
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{
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return uniphier_memconf_decode(dram_map, 0xa0000000, false);
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}
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static int uniphier_pxs2_dram_map_get(struct uniphier_dram_map dram_map[])
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{
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return uniphier_memconf_decode(dram_map, 0xc0000000, true);
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}
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struct uniphier_dram_init_data {
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unsigned int soc_id;
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int (*dram_map_get)(struct uniphier_dram_map dram_map[]);
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};
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static const struct uniphier_dram_init_data uniphier_dram_init_data[] = {
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{
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.soc_id = UNIPHIER_LD4_ID,
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.dram_map_get = uniphier_ld4_dram_map_get,
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},
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{
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.soc_id = UNIPHIER_PRO4_ID,
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.dram_map_get = uniphier_pro4_dram_map_get,
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},
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{
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.soc_id = UNIPHIER_SLD8_ID,
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.dram_map_get = uniphier_ld4_dram_map_get,
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},
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{
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.soc_id = UNIPHIER_PRO5_ID,
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.dram_map_get = uniphier_ld4_dram_map_get,
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},
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{
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.soc_id = UNIPHIER_PXS2_ID,
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.dram_map_get = uniphier_pxs2_dram_map_get,
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},
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{
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.soc_id = UNIPHIER_LD6B_ID,
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.dram_map_get = uniphier_pxs2_dram_map_get,
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},
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{
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.soc_id = UNIPHIER_LD11_ID,
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.dram_map_get = uniphier_ld4_dram_map_get,
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},
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{
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.soc_id = UNIPHIER_LD20_ID,
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.dram_map_get = uniphier_pxs2_dram_map_get,
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},
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{
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.soc_id = UNIPHIER_PXS3_ID,
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.dram_map_get = uniphier_pxs2_dram_map_get,
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},
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};
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UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_dram_init_data,
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uniphier_dram_init_data)
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static int uniphier_dram_map_get(struct uniphier_dram_map *dram_map)
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{
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const struct uniphier_dram_init_data *data;
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data = uniphier_get_dram_init_data();
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if (!data) {
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pr_err("unsupported SoC\n");
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return -ENOTSUPP;
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}
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return data->dram_map_get(dram_map);
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}
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int dram_init(void)
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{
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struct uniphier_dram_map dram_map[3] = {};
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bool valid_bank_found = false;
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unsigned long prev_top;
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int ret, i;
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gd->ram_size = 0;
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ret = uniphier_dram_map_get(dram_map);
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if (ret)
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return ret;
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for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
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unsigned long max_size;
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if (!dram_map[i].size)
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continue;
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/*
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* U-Boot relocates itself to the tail of the memory region,
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* but it does not expect sparse memory. We use the first
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* contiguous chunk here.
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*/
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if (valid_bank_found && prev_top < dram_map[i].base)
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break;
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/*
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* Do not use memory that exceeds 32bit address range. U-Boot
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* relocates itself to the end of the effectively available RAM.
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* This could be a problem for DMA engines that do not support
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* 64bit address (SDMA of SDHCI, UniPhier AV-ether, etc.)
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*/
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if (dram_map[i].base >= 1ULL << 32)
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break;
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max_size = (1ULL << 32) - dram_map[i].base;
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gd->ram_size = min(dram_map[i].size, max_size);
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if (!valid_bank_found)
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gd->ram_base = dram_map[i].base;
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prev_top = dram_map[i].base + dram_map[i].size;
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valid_bank_found = true;
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}
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/*
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* LD20 uses the last 64 byte for each channel for dynamic
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* DDR PHY training
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*/
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if (uniphier_get_soc_id() == UNIPHIER_LD20_ID)
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gd->ram_size -= 64;
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return 0;
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}
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int dram_init_banksize(void)
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{
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struct uniphier_dram_map dram_map[3] = {};
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unsigned long base, top;
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bool valid_bank_found = false;
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int ret, i;
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ret = uniphier_dram_map_get(dram_map);
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if (ret)
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return ret;
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for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
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if (i < ARRAY_SIZE(gd->bd->bi_dram)) {
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gd->bd->bi_dram[i].start = dram_map[i].base;
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gd->bd->bi_dram[i].size = dram_map[i].size;
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}
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if (!dram_map[i].size)
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continue;
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if (!valid_bank_found)
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base = dram_map[i].base;
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top = dram_map[i].base + dram_map[i].size;
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valid_bank_found = true;
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}
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if (!valid_bank_found)
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return -EINVAL;
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/* map all the DRAM regions */
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uniphier_mem_map_init(base, top - base);
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return 0;
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}
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