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https://github.com/brain-hackers/u-boot-brain
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8ec293e063
H616 is very similar to H6 so most of the infrastructure can be reused. However, two big differences are that it doesn't have functional SRAM A2 which is usually used for TF-A and it doesn't have ARISC co-processor. It also needs bigger SPL size - 48 KiB. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
171 lines
4.4 KiB
C
171 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <axp_pmic.h>
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#include <errno.h>
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#ifdef CONFIG_MACH_SUN6I
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int sunxi_get_ss_bonding_id(void)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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static int bonding_id = -1;
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if (bonding_id != -1)
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return bonding_id;
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/* Enable Security System */
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setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS);
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setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS);
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bonding_id = readl(SUNXI_SS_BASE);
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bonding_id = (bonding_id >> 16) & 0x7;
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/* Disable Security System again */
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clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS);
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clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS);
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return bonding_id;
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}
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#endif
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#ifdef CONFIG_MACH_SUN8I
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uint sunxi_get_sram_id(void)
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{
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uint id;
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/* Unlock sram info reg, read it, relock */
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setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
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id = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
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clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
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return id;
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}
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#endif
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#ifdef CONFIG_DISPLAY_CPUINFO
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int print_cpuinfo(void)
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{
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#ifdef CONFIG_MACH_SUN4I
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puts("CPU: Allwinner A10 (SUN4I)\n");
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#elif defined CONFIG_MACH_SUN5I
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u32 val = readl(SUNXI_SID_BASE + 0x08);
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switch ((val >> 12) & 0xf) {
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case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break;
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case 3: puts("CPU: Allwinner A13 (SUN5I)\n"); break;
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case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break;
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default: puts("CPU: Allwinner A1X (SUN5I)\n");
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}
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#elif defined CONFIG_MACH_SUN6I
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switch (sunxi_get_ss_bonding_id()) {
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case SUNXI_SS_BOND_ID_A31:
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puts("CPU: Allwinner A31 (SUN6I)\n");
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break;
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case SUNXI_SS_BOND_ID_A31S:
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puts("CPU: Allwinner A31s (SUN6I)\n");
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break;
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default:
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printf("CPU: Allwinner A31? (SUN6I, id: %d)\n",
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sunxi_get_ss_bonding_id());
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}
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#elif defined CONFIG_MACH_SUN7I
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puts("CPU: Allwinner A20 (SUN7I)\n");
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#elif defined CONFIG_MACH_SUN8I_A23
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printf("CPU: Allwinner A23 (SUN8I %04x)\n", sunxi_get_sram_id());
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#elif defined CONFIG_MACH_SUN8I_A33
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printf("CPU: Allwinner A33 (SUN8I %04x)\n", sunxi_get_sram_id());
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#elif defined CONFIG_MACH_SUN8I_A83T
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printf("CPU: Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id());
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#elif defined CONFIG_MACH_SUN8I_H3
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printf("CPU: Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
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#elif defined CONFIG_MACH_SUN8I_R40
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printf("CPU: Allwinner R40 (SUN8I %04x)\n", sunxi_get_sram_id());
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#elif defined CONFIG_MACH_SUN8I_V3S
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printf("CPU: Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
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#elif defined CONFIG_MACH_SUN9I
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puts("CPU: Allwinner A80 (SUN9I)\n");
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#elif defined CONFIG_MACH_SUN50I
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puts("CPU: Allwinner A64 (SUN50I)\n");
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#elif defined CONFIG_MACH_SUN50I_H5
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puts("CPU: Allwinner H5 (SUN50I)\n");
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#elif defined CONFIG_MACH_SUN50I_H6
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puts("CPU: Allwinner H6 (SUN50I)\n");
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#elif defined CONFIG_MACH_SUN50I_H616
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puts("CPU: Allwinner H616 (SUN50I)\n");
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#else
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#warning Please update cpu_info.c with correct CPU information
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puts("CPU: SUNXI Family\n");
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#endif
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return 0;
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}
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#endif
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#ifdef CONFIG_MACH_SUN8I_H3
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#define SIDC_PRCTL 0x40
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#define SIDC_RDKEY 0x60
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#define SIDC_OP_LOCK 0xAC
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uint32_t sun8i_efuse_read(uint32_t offset)
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{
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uint32_t reg_val;
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reg_val = readl(SUNXI_SIDC_BASE + SIDC_PRCTL);
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reg_val &= ~(((0x1ff) << 16) | 0x3);
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reg_val |= (offset << 16);
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writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL);
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reg_val &= ~(((0xff) << 8) | 0x3);
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reg_val |= (SIDC_OP_LOCK << 8) | 0x2;
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writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL);
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while (readl(SUNXI_SIDC_BASE + SIDC_PRCTL) & 0x2);
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reg_val &= ~(((0x1ff) << 16) | ((0xff) << 8) | 0x3);
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writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL);
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reg_val = readl(SUNXI_SIDC_BASE + SIDC_RDKEY);
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return reg_val;
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}
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#endif
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int sunxi_get_sid(unsigned int *sid)
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{
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#ifdef CONFIG_AXP221_POWER
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return axp_get_sid(sid);
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#elif defined CONFIG_MACH_SUN8I_H3
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/*
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* H3 SID controller has a bug, which makes the initial value of
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* SUNXI_SID_BASE at boot wrong.
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* Read the value directly from SID controller, in order to get
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* the correct value, and also refresh the wrong value at
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* SUNXI_SID_BASE.
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*/
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int i;
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for (i = 0; i< 4; i++)
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sid[i] = sun8i_efuse_read(i * 4);
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return 0;
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#elif defined SUNXI_SID_BASE
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int i;
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for (i = 0; i< 4; i++)
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sid[i] = readl((ulong)SUNXI_SID_BASE + 4 * i);
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return 0;
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#else
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return -ENODEV;
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#endif
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}
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