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https://github.com/brain-hackers/u-boot-brain
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2fd1dc5593
Move Stratix10 and Agilex system manager common code to system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
108 lines
3.2 KiB
C
108 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
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*
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*/
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#include <asm/io.h>
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#include <common.h>
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#include <asm/arch/firewall.h>
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#include <asm/arch/system_manager.h>
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static void firewall_l4_per_disable(void)
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{
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const struct socfpga_firwall_l4_per *firwall_l4_per_base =
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(struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
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u32 i;
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const u32 *addr[] = {
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&firwall_l4_per_base->nand,
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&firwall_l4_per_base->nand_data,
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&firwall_l4_per_base->usb0,
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&firwall_l4_per_base->usb1,
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&firwall_l4_per_base->spim0,
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&firwall_l4_per_base->spim1,
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&firwall_l4_per_base->emac0,
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&firwall_l4_per_base->emac1,
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&firwall_l4_per_base->emac2,
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&firwall_l4_per_base->sdmmc,
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&firwall_l4_per_base->gpio0,
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&firwall_l4_per_base->gpio1,
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&firwall_l4_per_base->i2c0,
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&firwall_l4_per_base->i2c1,
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&firwall_l4_per_base->i2c2,
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&firwall_l4_per_base->i2c3,
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&firwall_l4_per_base->i2c4,
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&firwall_l4_per_base->timer0,
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&firwall_l4_per_base->timer1,
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&firwall_l4_per_base->uart0,
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&firwall_l4_per_base->uart1
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};
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/*
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* The following lines of code will enable non-secure access
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* to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This
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* is needed as most OS run in non-secure mode. Thus we need to
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* enable non-secure access to these peripherals in order for the
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* OS to use these peripherals.
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*/
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for (i = 0; i < ARRAY_SIZE(addr); i++)
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writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
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}
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static void firewall_l4_sys_disable(void)
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{
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const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
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(struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
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u32 i;
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const u32 *addr[] = {
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&firwall_l4_sys_base->dma_ecc,
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&firwall_l4_sys_base->emac0rx_ecc,
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&firwall_l4_sys_base->emac0tx_ecc,
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&firwall_l4_sys_base->emac1rx_ecc,
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&firwall_l4_sys_base->emac1tx_ecc,
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&firwall_l4_sys_base->emac2rx_ecc,
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&firwall_l4_sys_base->emac2tx_ecc,
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&firwall_l4_sys_base->nand_ecc,
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&firwall_l4_sys_base->nand_read_ecc,
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&firwall_l4_sys_base->nand_write_ecc,
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&firwall_l4_sys_base->ocram_ecc,
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&firwall_l4_sys_base->sdmmc_ecc,
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&firwall_l4_sys_base->usb0_ecc,
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&firwall_l4_sys_base->usb1_ecc,
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&firwall_l4_sys_base->clock_manager,
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&firwall_l4_sys_base->io_manager,
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&firwall_l4_sys_base->reset_manager,
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&firwall_l4_sys_base->system_manager,
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&firwall_l4_sys_base->watchdog0,
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&firwall_l4_sys_base->watchdog1,
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&firwall_l4_sys_base->watchdog2,
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&firwall_l4_sys_base->watchdog3
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};
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for (i = 0; i < ARRAY_SIZE(addr); i++)
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writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
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}
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static void firewall_bridge_disable(void)
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{
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/* disable lwsocf2fpga and soc2fpga bridge security */
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writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);
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writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);
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}
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void firewall_setup(void)
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{
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firewall_l4_per_disable();
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firewall_l4_sys_disable();
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firewall_bridge_disable();
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/* disable SMMU security */
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writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
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/* enable non-secure interface to DMA330 DMA and peripherals */
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writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS,
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socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA);
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writel(SYSMGR_DMAPERIPH_ALL_NS,
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socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA_PERIPH);
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}
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