mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
1bc20897c1
Vendor Authorized Boot is a security feature for authenticating the images such as U-Boot, ARM trusted Firmware, Linux kernel, device tree blob and etc loaded from FIT. After those images are loaded from FIT, the VAB certificate and signature block appended at the end of each image are sent to Secure Device Manager (SDM) for authentication. U-Boot will validate the SHA384 of the image against the SHA384 hash stored in the VAB certificate before sending the image to SDM for authentication. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
235 lines
6.6 KiB
Plaintext
235 lines
6.6 KiB
Plaintext
if ARCH_SOCFPGA
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config ERR_PTR_OFFSET
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default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
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config NR_DRAM_BANKS
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default 1
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config SOCFPGA_SECURE_VAB_AUTH
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bool "Enable boot image authentication with Secure Device Manager"
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depends on TARGET_SOCFPGA_AGILEX
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select FIT_IMAGE_POST_PROCESS
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select SHA384
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select SHA512_ALGO
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select SPL_FIT_IMAGE_POST_PROCESS
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help
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All images loaded from FIT will be authenticated by Secure Device
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Manager.
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config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE
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bool "Allow non-FIT VAB signed images"
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depends on SOCFPGA_SECURE_VAB_AUTH
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config SPL_SIZE_LIMIT
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default 0x10000 if TARGET_SOCFPGA_GEN5
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config SPL_SIZE_LIMIT_PROVIDE_STACK
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default 0x200 if TARGET_SOCFPGA_GEN5
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config SPL_STACK_R_ADDR
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default 0x00800000 if TARGET_SOCFPGA_GEN5
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config SPL_SYS_MALLOC_F_LEN
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default 0x800 if TARGET_SOCFPGA_GEN5
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config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
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default 0xa2
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config SYS_MALLOC_F_LEN
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default 0x2000 if TARGET_SOCFPGA_ARRIA10
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default 0x2000 if TARGET_SOCFPGA_GEN5
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config SYS_TEXT_BASE
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default 0x01000040 if TARGET_SOCFPGA_ARRIA10
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default 0x01000040 if TARGET_SOCFPGA_GEN5
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config TARGET_SOCFPGA_AGILEX
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bool
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select ARMV8_MULTIENTRY
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select ARMV8_SET_SMPEN
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select BINMAN if SPL_ATF
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select CLK
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select FPGA_INTEL_SDM_MAILBOX
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select NCORE_CACHE
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select SPL_CLK if SPL
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select TARGET_SOCFPGA_SOC64
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config TARGET_SOCFPGA_ARRIA5
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bool
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select TARGET_SOCFPGA_GEN5
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config TARGET_SOCFPGA_ARRIA10
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bool
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select SPL_ALTERA_SDRAM
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select SPL_BOARD_INIT if SPL
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select SPL_CACHE if SPL
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select CLK
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select SPL_CLK if SPL
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select DM_I2C
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select DM_RESET
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select SPL_DM_RESET if SPL
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select REGMAP
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select SPL_REGMAP if SPL
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select SYSCON
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select SPL_SYSCON if SPL
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select ETH_DESIGNWARE_SOCFPGA
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imply FPGA_SOCFPGA
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imply SPL_USE_TINY_PRINTF
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config TARGET_SOCFPGA_CYCLONE5
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bool
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select TARGET_SOCFPGA_GEN5
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config TARGET_SOCFPGA_GEN5
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bool
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select SPL_ALTERA_SDRAM
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imply FPGA_SOCFPGA
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imply SPL_SIZE_LIMIT_SUBTRACT_GD
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imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
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imply SPL_STACK_R
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imply SPL_SYS_MALLOC_SIMPLE
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imply SPL_USE_TINY_PRINTF
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config TARGET_SOCFPGA_SOC64
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bool
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config TARGET_SOCFPGA_STRATIX10
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bool
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select ARMV8_MULTIENTRY
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select ARMV8_SET_SMPEN
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select BINMAN if SPL_ATF
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select FPGA_INTEL_SDM_MAILBOX
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select TARGET_SOCFPGA_SOC64
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choice
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prompt "Altera SOCFPGA board select"
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optional
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config TARGET_SOCFPGA_AGILEX_SOCDK
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bool "Intel SOCFPGA SoCDK (Agilex)"
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select TARGET_SOCFPGA_AGILEX
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config TARGET_SOCFPGA_ARIES_MCVEVK
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bool "Aries MCVEVK (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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config TARGET_SOCFPGA_ARRIA10_SOCDK
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bool "Altera SOCFPGA SoCDK (Arria 10)"
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select TARGET_SOCFPGA_ARRIA10
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config TARGET_SOCFPGA_ARRIA5_SECU1
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bool "ABB SECU1 (Arria V)"
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select TARGET_SOCFPGA_ARRIA5
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select VENDOR_KM
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config TARGET_SOCFPGA_ARRIA5_SOCDK
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bool "Altera SOCFPGA SoCDK (Arria V)"
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select TARGET_SOCFPGA_ARRIA5
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config TARGET_SOCFPGA_CYCLONE5_SOCDK
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bool "Altera SOCFPGA SoCDK (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
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bool "Devboards DBM-SoC1 (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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config TARGET_SOCFPGA_EBV_SOCRATES
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bool "EBV SoCrates (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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config TARGET_SOCFPGA_IS1
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bool "IS1 (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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config TARGET_SOCFPGA_SOFTING_VINING_FPGA
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bool "Softing VIN|ING FPGA (Cyclone V)"
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select BOARD_LATE_INIT
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select TARGET_SOCFPGA_CYCLONE5
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config TARGET_SOCFPGA_SR1500
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bool "SR1500 (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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config TARGET_SOCFPGA_STRATIX10_SOCDK
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bool "Intel SOCFPGA SoCDK (Stratix 10)"
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select TARGET_SOCFPGA_STRATIX10
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config TARGET_SOCFPGA_TERASIC_DE0_NANO
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bool "Terasic DE0-Nano-Atlas (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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config TARGET_SOCFPGA_TERASIC_DE10_NANO
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bool "Terasic DE10-Nano (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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config TARGET_SOCFPGA_TERASIC_DE1_SOC
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bool "Terasic DE1-SoC (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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config TARGET_SOCFPGA_TERASIC_SOCKIT
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bool "Terasic SoCkit (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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endchoice
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config SYS_BOARD
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default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
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default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
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default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
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default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
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default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
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default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
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default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
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default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
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default "is1" if TARGET_SOCFPGA_IS1
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default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
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default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
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default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
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default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
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default "sr1500" if TARGET_SOCFPGA_SR1500
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default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
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default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
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config SYS_VENDOR
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default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
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default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
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default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
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default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
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default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
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default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
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default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
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default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
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default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
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default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
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default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
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default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
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default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
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default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
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config SYS_SOC
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default "socfpga"
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config SYS_CONFIG_NAME
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default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
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default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
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default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
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default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
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default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
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default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
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default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
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default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
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default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
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default "socfpga_is1" if TARGET_SOCFPGA_IS1
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default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
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default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
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default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
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default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
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default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
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default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
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source "board/keymile/Kconfig"
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endif
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