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https://github.com/brain-hackers/u-boot-brain
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35b65dd8ef
Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to. This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value. Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g. COLD vs WARM resets). As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely. Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.
This transformation was done with the following coccinelle patch:
@@
expression argvalue;
@@
- reset_cpu(argvalue)
+ reset_cpu()
@@
identifier argname;
type argtype;
@@
- reset_cpu(argtype argname)
+ reset_cpu(void)
{ ... }
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
78 lines
1.7 KiB
C
78 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* https://spdx.org/licenses
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*/
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#include <common.h>
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#include <asm/armv8/mmu.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/board.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define OTX_MEM_MAP_USED 3
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/* 1 for 83xx, +1 is end of list which needs to be empty */
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#define OTX_MEM_MAP_MAX (OTX_MEM_MAP_USED + 1 + CONFIG_NR_DRAM_BANKS + 1)
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static struct mm_region otx_mem_map[OTX_MEM_MAP_MAX] = {
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{
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.virt = 0x800000000000UL,
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.phys = 0x800000000000UL,
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.size = 0x40000000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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}, {
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.virt = 0x840000000000UL,
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.phys = 0x840000000000UL,
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.size = 0x40000000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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}, {
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.virt = 0x880000000000UL,
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.phys = 0x880000000000UL,
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.size = 0x40000000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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}
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};
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struct mm_region *mem_map = otx_mem_map;
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void mem_map_fill(void)
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{
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int banks = OTX_MEM_MAP_USED;
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u32 dram_start = CONFIG_SYS_TEXT_BASE;
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if (otx_is_soc(CN83XX)) {
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otx_mem_map[banks].virt = 0x8c0000000000UL;
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otx_mem_map[banks].phys = 0x8c0000000000UL;
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otx_mem_map[banks].size = 0x40000000000UL;
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otx_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE;
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banks = banks + 1;
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}
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for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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otx_mem_map[banks].virt = dram_start;
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otx_mem_map[banks].phys = dram_start;
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otx_mem_map[banks].size = gd->ram_size;
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otx_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_NON_SHARE;
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banks = banks + 1;
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}
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}
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u64 get_page_table_size(void)
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{
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return 0x80000;
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}
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void reset_cpu(void)
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{
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}
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