mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
b3d9a8b185
Following the example of most other SoCs in arch/$(ARCH)/cpu/$(CPU)/$(SOC)
move the lpc32xx code from arch/arm/cpu/arm926ejs/lpc32xx to
arch/arm/mach-lpc32xx.
Following the checklist from
commit 01f1445630 ("ARM: prepare for moving SoC sources into mach-*"):
[1] move files from arch/arm/cpu/arm926ejs/lpc32xx to arch/arm/mach-lpx32xx
[2] add machine entry to arch/arm/Makefile
[3] remove "obj-y += ..." from arch/arm/cpu/arm926ejs/Makefile
[4] fix the Kconfig file path in arch/arm/Kconfig
[5] (no MAINTAINERS update)
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
45 lines
1000 B
ArmAsm
45 lines
1000 B
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* WORK Microwave work_92105 board low level init
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*
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* (C) Copyright 2014 DENX Software Engineering GmbH
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* Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
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*
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* Low level init is called from SPL to set up the clocks.
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* On entry, the LPC3250 is in Direct Run mode with all clocks
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* running at 13 MHz; on exit, ARM clock is 208 MHz, HCLK is
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* 104 MHz and PCLK is 13 MHz.
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*
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* This code must run from SRAM so that the clock changes do
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* not prevent it from executing.
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*/
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.globl lowlevel_init
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lowlevel_init:
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/* Set ARM, HCLK, PCLK dividers for normal mode */
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ldr r0, =0x0000003D
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ldr r1, =0x40004040
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str r0, [r1]
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/* Start HCLK PLL for 208 MHz */
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ldr r0, =0x0001401E
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ldr r1, =0x40004058
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str r0, [r1]
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/* wait for HCLK PLL to lock */
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1:
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ldr r0, [r1]
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ands r0, r0, #1
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beq 1b
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/* switch to normal mode */
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ldr r1, =0x40004044
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ldr r0, [r1]
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orr r0, #0x00000004
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str r0, [r1]
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/* Return to U-Boot via saved link register */
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mov pc, lr
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