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d9fba73a88
i.MX7ULP uses the same MMDC controller IP as found on i.MX53 and i.MX6, so build mmdc_size.c for i.MX7ULP as well. Signed-off-by: Fabio Estevam <festevam@gmail.com>
58 lines
1.7 KiB
C
58 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include <common.h>
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#include <asm/io.h>
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#if defined(CONFIG_MX53)
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#define MEMCTL_BASE ESDCTL_BASE_ADDR
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#elif defined(CONFIG_MX6)
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#define MEMCTL_BASE MMDC_P0_BASE_ADDR
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#elif defined(CONFIG_MX7ULP)
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#define MEMCTL_BASE MMDC0_RBASE
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#endif
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static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
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static const unsigned char bank_lookup[] = {3, 2};
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/* these MMDC registers are common to the IMX53 and IMX6 */
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struct esd_mmdc_regs {
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u32 ctl;
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u32 pdc;
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u32 otc;
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u32 cfg0;
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u32 cfg1;
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u32 cfg2;
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u32 misc;
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};
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#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
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#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
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#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
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#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
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#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
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/*
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* imx_ddr_size - return size in bytes of DRAM according MMDC config
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* The MMDC MDCTL register holds the number of bits for row, col, and data
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* width and the MMDC MDMISC register holds the number of banks. Combine
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* all these bits to determine the meme size the MMDC has been configured for
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*/
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unsigned int imx_ddr_size(void)
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{
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struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
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unsigned int ctl = readl(&mem->ctl);
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unsigned int misc = readl(&mem->misc);
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int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
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bits += ESD_MMDC_CTL_GET_ROW(ctl);
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bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
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bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
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bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
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bits += ESD_MMDC_CTL_GET_CS1(ctl);
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/* The MX6 can do only 3840 MiB of DRAM */
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if (bits == 32)
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return 0xf0000000;
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return 1 << bits;
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}
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