mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
128 lines
3.6 KiB
ArmAsm
128 lines
3.6 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013 Samsung Electronics
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* Akshay Saraswat <akshay.s@samsung.com>
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*/
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#include <config.h>
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#include <asm/arch/cpu.h>
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.globl relocate_wait_code
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relocate_wait_code:
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adr r0, code_base @ r0: source address (start)
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adr r1, code_end @ r1: source address (end)
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ldr r2, =0x02073000 @ r2: target address
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1:
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ldmia r0!, {r3-r6}
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stmia r2!, {r3-r6}
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cmp r0, r1
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blt 1b
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b code_end
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.ltorg
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/*
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* Secondary core waits here until Primary wake it up.
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* Below code is copied to CONFIG_EXYNOS_RELOCATE_CODE_BASE.
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* This is a workaround code which is supposed to act as a
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* substitute/supplement to the iROM code.
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*
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* This workaround code is relocated to the address 0x02073000
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* because that comes out to be the last 4KB of the iRAM
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* (Base Address - 0x02020000, Limit Address - 0x020740000).
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*
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* U-Boot and kernel are aware of this code and flags by the simple
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* fact that we are implementing a workaround in the last 4KB
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* of the iRAM and we have already defined these flag and address
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* values in both kernel and U-Boot for our use.
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*/
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code_base:
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b 1f
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/*
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* These addresses are being used as flags in u-boot and kernel.
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*
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* Jump address for resume and flag to check for resume/reset:
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* Resume address - 0x2073008
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* Resume flag - 0x207300C
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*
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* Jump address for cluster switching:
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* Switch address - 0x2073018
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*
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* Jump address for core hotplug:
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* Hotplug address - 0x207301C
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*
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* Jump address for C2 state (Reserved for future not being used right now):
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* C2 address - 0x2073024
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*
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* Managed per core status for the active cluster:
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* CPU0 state - 0x2073028
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* CPU1 state - 0x207302C
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* CPU2 state - 0x2073030
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* CPU3 state - 0x2073034
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*
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* Managed per core GIC status for the active cluster:
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* CPU0 gic state - 0x2073038
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* CPU1 gic state - 0x207303C
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* CPU2 gic state - 0x2073040
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* CPU3 gic state - 0x2073044
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*
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* Logic of the code:
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* Step-1: Read current CPU status.
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* Step-2: If it's a resume then continue, else jump to step 4.
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* Step-3: Clear inform1 PMU register and jump to inform0 value.
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* Step-4: If it's a switch, C2 or reset, get the hotplug address.
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* Step-5: If address is not available, enter WFE.
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* Step-6: If address is available, jump to that address.
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*/
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nop @ for backward compatibility
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.word 0x0 @ REG0: RESUME_ADDR
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.word 0x0 @ REG1: RESUME_FLAG
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.word 0x0 @ REG2
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.word 0x0 @ REG3
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_switch_addr:
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.word 0x0 @ REG4: SWITCH_ADDR
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_hotplug_addr:
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.word 0x0 @ REG5: CPU1_BOOT_REG
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.word 0x0 @ REG6
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_c2_addr:
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.word 0x0 @ REG7: REG_C2_ADDR
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_cpu_state:
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.word 0x1 @ CPU0_STATE : RESET
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.word 0x2 @ CPU1_STATE : SECONDARY RESET
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.word 0x2 @ CPU2_STATE : SECONDARY RESET
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.word 0x2 @ CPU3_STATE : SECONDARY RESET
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_gic_state:
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.word 0x0 @ CPU0 - GICD_IGROUPR0
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.word 0x0 @ CPU1 - GICD_IGROUPR0
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.word 0x0 @ CPU2 - GICD_IGROUPR0
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.word 0x0 @ CPU3 - GICD_IGROUPR0
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1:
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adr r0, _cpu_state
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mrc p15, 0, r7, c0, c0, 5 @ read MPIDR
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and r7, r7, #0xf @ r7 = cpu id
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/* Read the current cpu state */
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ldr r10, [r0, r7, lsl #2]
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svc_entry:
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tst r10, #(1 << 4)
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adrne r0, _switch_addr
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bne wait_for_addr
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/* Clear INFORM1 */
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ldr r0, =(0x10040000 + 0x804)
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ldr r1, [r0]
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cmp r1, #0x0
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movne r1, #0x0
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strne r1, [r0]
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/* Get INFORM0 */
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ldrne r1, =(0x10040000 + 0x800)
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ldrne pc, [r1]
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tst r10, #(1 << 0)
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ldrne pc, =0x23e00000
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adr r0, _hotplug_addr
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wait_for_addr:
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ldr r1, [r0]
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cmp r1, #0x0
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bxne r1
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wfe
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b wait_for_addr
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.ltorg
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code_end:
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mov pc, lr
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