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https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
234 lines
8.5 KiB
C
234 lines
8.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2008 Extreme Engineering Solutions, Inc.
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* Copyright 2008 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
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{
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i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
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sizeof(ddr2_spd_eeprom_t));
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}
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/*
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* There are four board-specific SDRAM timing parameters which must be
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* calculated based on the particular PCB artwork. These are:
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* 1.) CPO (Read Capture Delay)
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* - TIMING_CFG_2 register
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* Source: Calculation based on board trace lengths and
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* chip-specific internal delays.
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* 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
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* - TIMING_CFG_2 register
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* Source: Calculation based on board trace lengths.
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* Unless clock and DQ lanes are very different
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* lengths (>2"), this should be set to the nominal value
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* of 1/2 clock delay.
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* 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
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* - DDR_SDRAM_CLK_CNTL register
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* Source: Signal Integrity Simulations
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* 4.) 2T Timing on Addr/Ctl
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* - TIMING_CFG_2 register
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* Source: Signal Integrity Simulations
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* Usually only needed with heavy load/very high speed (>DDR2-800)
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*
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* ====== XPedite5370 DDR2-600 read delay calculations ======
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*
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* See Freescale's App Note AN2583 as refrence. This document also
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* contains the chip-specific delays for 8548E, 8572, etc.
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*
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* For MPC8572E
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* Minimum chip delay (Ch 0): 1.372ns
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* Maximum chip delay (Ch 0): 2.914ns
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* Minimum chip delay (Ch 1): 1.220ns
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* Maximum chip delay (Ch 1): 2.595ns
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*
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* CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps
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*
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* Minimum delay calc (Ch 0):
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* clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
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* 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps
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* = 3808ps
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* = 3.808ns
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*
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* Maximum delay calc (Ch 0):
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* clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
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* 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps
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* = 6240ps
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* = 6.240ns
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*
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* Minimum delay calc (Ch 1):
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* clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
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* 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps
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* = 3288ps
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* = 3.288ns
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*
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* Maximum delay calc (Ch 1):
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* clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
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* 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps
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* = 5536ps
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* = 5.536ns
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*
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* Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target)
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* This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
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* Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target)
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* This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7)
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*
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*
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* ====== XPedite5370 DDR2-800 read delay calculations ======
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*
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* See Freescale's App Note AN2583 as refrence. This document also
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* contains the chip-specific delays for 8548E, 8572, etc.
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*
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* For MPC8572E
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* Minimum chip delay (Ch 0): 1.372ns
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* Maximum chip delay (Ch 0): 2.914ns
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* Minimum chip delay (Ch 1): 1.220ns
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* Maximum chip delay (Ch 1): 2.595ns
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*
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* CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps
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*
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* Minimum delay calc (Ch 0):
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* clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
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* 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps
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* = 3341ps
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* = 3.341ns
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*
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* Maximum delay calc (Ch 0):
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* clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
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* 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps
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* = 5673ps
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* = 5.673ns
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*
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* Minimum delay calc (Ch 1):
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* clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
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* 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps
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* = 2822ps
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* = 2.822ns
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*
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* Maximum delay calc (Ch 1):
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* clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
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* 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps
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* = 4968ps
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* = 4.968ns
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*
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* Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target)
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* This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9)
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* Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target)
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* This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
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*
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* Write latency (WR_DATA_DELAY) is calculated by doing the following:
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*
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* The DDR SDRAM specification requires DQS be received no sooner than
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* 75% of an SDRAM clock period—and no later than 125% of a clock
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* period—from the capturing clock edge of the command/address at the
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* SDRAM.
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*
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* Based on the above tracelengths, the following are calculated:
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* Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns
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* Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns
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* Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns
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* Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns
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*
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* Difference in arrival time CLK vs. DQS:
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* Ch. 0 0.072ns
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* Ch. 1 0.138ns
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*
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* Both of these values are much less than 25% of the clock
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* period at DDR2-600 or DDR2-800, so no additional delay is needed over
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* the 1/2 cycle which normally aligns the first DQS transition
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* exactly WL (CAS latency minus one cycle) after the CAS strobe.
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* See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
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* terminology corresponds to exactly one clock period delay after
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* the CAS strobe. (due to the fact that the "delay" is referenced
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* from the *falling* edge of the CLK, just after the rising edge
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* which the CAS strobe is latched on.
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*/
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typedef struct board_memctl_options {
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uint16_t datarate_mhz_low;
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uint16_t datarate_mhz_high;
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uint8_t clk_adjust;
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uint8_t cpo_override;
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uint8_t write_data_delay;
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} board_memctl_options_t;
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static struct board_memctl_options bopts_ctrl[][2] = {
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{
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/* Controller 0 */
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{
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/* DDR2 600/667 */
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.datarate_mhz_low = 500,
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.datarate_mhz_high = 750,
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.clk_adjust = 5,
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.cpo_override = 8,
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.write_data_delay = 2,
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},
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{
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/* DDR2 800 */
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.datarate_mhz_low = 750,
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.datarate_mhz_high = 850,
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.clk_adjust = 5,
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.cpo_override = 9,
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.write_data_delay = 2,
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},
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},
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{
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/* Controller 1 */
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{
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/* DDR2 600/667 */
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.datarate_mhz_low = 500,
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.datarate_mhz_high = 750,
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.clk_adjust = 5,
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.cpo_override = 7,
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.write_data_delay = 2,
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},
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{
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/* DDR2 800 */
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.datarate_mhz_low = 750,
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.datarate_mhz_high = 850,
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.clk_adjust = 5,
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.cpo_override = 8,
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.write_data_delay = 2,
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},
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},
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};
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
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sys_info_t sysinfo;
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int i;
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unsigned int datarate;
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get_sys_info(&sysinfo);
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datarate = sysinfo.freq_ddrbus / 1000 / 1000;
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for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
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if ((bopts[i].datarate_mhz_low <= datarate) &&
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(bopts[i].datarate_mhz_high >= datarate)) {
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debug("controller %d:\n", ctrl_num);
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debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
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debug(" cpo = %d\n", bopts[i].cpo_override);
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debug(" write_data_delay = %d\n",
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bopts[i].write_data_delay);
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popts->clk_adjust = bopts[i].clk_adjust;
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popts->cpo_override = bopts[i].cpo_override;
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popts->write_data_delay = bopts[i].write_data_delay;
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}
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}
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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}
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