mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
163 lines
3.8 KiB
C
163 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2008
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* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
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*/
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#include <common.h>
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#if defined(CONFIG_SYS_NAND_BASE)
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#include <nand.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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static int state;
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static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte);
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static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
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static u_char sc_nand_read_byte(struct mtd_info *mtd);
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static u16 sc_nand_read_word(struct mtd_info *mtd);
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static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
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static int sc_nand_device_ready(struct mtd_info *mtdinfo);
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#define FPGA_NAND_CMD_MASK (0x7 << 28)
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#define FPGA_NAND_CMD_COMMAND (0x0 << 28)
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#define FPGA_NAND_CMD_ADDR (0x1 << 28)
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#define FPGA_NAND_CMD_READ (0x2 << 28)
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#define FPGA_NAND_CMD_WRITE (0x3 << 28)
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#define FPGA_NAND_BUSY (0x1 << 15)
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#define FPGA_NAND_ENABLE (0x1 << 31)
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#define FPGA_NAND_DATA_SHIFT 16
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/**
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* sc_nand_write_byte - write one byte to the chip
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* @mtd: MTD device structure
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* @byte: pointer to data byte to write
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*/
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static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte)
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{
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sc_nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte));
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}
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/**
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* sc_nand_write_buf - write buffer to chip
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*/
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static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd_to_nand(mtd);
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for (i = 0; i < len; i++) {
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out_be32(this->IO_ADDR_W,
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state | (buf[i] << FPGA_NAND_DATA_SHIFT));
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}
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}
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/**
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* sc_nand_read_byte - read one byte from the chip
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* @mtd: MTD device structure
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*/
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static u_char sc_nand_read_byte(struct mtd_info *mtd)
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{
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u8 byte;
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sc_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
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return byte;
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}
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/**
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* sc_nand_read_word - read one word from the chip
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* @mtd: MTD device structure
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*/
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static u16 sc_nand_read_word(struct mtd_info *mtd)
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{
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u16 word;
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sc_nand_read_buf(mtd, (uchar *)&word, sizeof(word));
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return word;
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}
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/**
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* sc_nand_read_buf - read chip data into buffer
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* @mtd: MTD device structure
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* @buf: buffer to store date
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* @len: number of bytes to read
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*/
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static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd_to_nand(mtd);
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int val;
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val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ;
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out_be32(this->IO_ADDR_W, val);
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for (i = 0; i < len; i++) {
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buf[i] = (in_be32(this->IO_ADDR_R) >> FPGA_NAND_DATA_SHIFT) & 0xff;
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}
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}
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/**
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* sc_nand_device_ready - Check the NAND device is ready for next command.
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* @mtd: MTD device structure
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*/
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static int sc_nand_device_ready(struct mtd_info *mtdinfo)
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{
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struct nand_chip *this = mtd_to_nand(mtdinfo);
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if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY)
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return 0; /* busy */
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return 1;
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}
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/**
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* sc_nand_hwcontrol - NAND control functions wrapper.
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* @mtd: MTD device structure
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* @cmd: Command
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*/
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static void sc_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
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{
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if (ctrl & NAND_CTRL_CHANGE) {
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state &= ~(FPGA_NAND_CMD_MASK | FPGA_NAND_ENABLE);
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switch (ctrl & (NAND_ALE | NAND_CLE)) {
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case 0:
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state |= FPGA_NAND_CMD_WRITE;
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break;
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case NAND_ALE:
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state |= FPGA_NAND_CMD_ADDR;
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break;
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case NAND_CLE:
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state |= FPGA_NAND_CMD_COMMAND;
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break;
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default:
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printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl);
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}
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if (ctrl & NAND_NCE)
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state |= FPGA_NAND_ENABLE;
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}
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if (cmd != NAND_CMD_NONE)
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sc_nand_write_byte(mtdinfo, cmd);
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}
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int board_nand_init(struct nand_chip *nand)
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{
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nand->cmd_ctrl = sc_nand_hwcontrol;
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nand->ecc.mode = NAND_ECC_SOFT;
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nand->dev_ready = sc_nand_device_ready;
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nand->read_byte = sc_nand_read_byte;
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nand->read_word = sc_nand_read_word;
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nand->write_buf = sc_nand_write_buf;
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nand->read_buf = sc_nand_read_buf;
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return 0;
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}
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#endif
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